URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_reg.xml] - Diff between revs 131 and 134

Rev 131	Rev 134
Line 75...	Line 75...











`fs-sim`


	`gen_verilog`
	`104.0`
	`none`
	`common`
	`./tools/verilog/gen_verilog`


	`destination`
	`jtag_classic_rpc_reg`





`dest_dir`
`../verilog/`
`verilogSourcelibraryDir`






`fs-syn`


`dest_dir`
`../verilog/`
`verilogSourcelibraryDir`









`fs-lint`

`dest_dir../verilog/`
`verilogSourcelibraryDir`









	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`






	`commoncommon`
	`Verilog`


	`fs-common`







Line 168...	Line 170...












	`fs-common`



	`../verilog/classic_rpc_reg`
	`verilogSourcefragment`





	`../verilog/copyright`
	`verilogSourceinclude`







	`fs-sim`




	`../verilog/common/jtag_classic_rpc_reg`
	`verilogSourcemodule`




	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`






	`fs-syn`



	`../verilog/common/jtag_classic_rpc_reg`
	`verilogSourcemodule`




	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`









	`fs-lint`



	`../verilog/common/jtag_classic_rpc_reg`
	`verilogSourcemodule`





	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`











`BITS16`	`BITS16`
`RESET_VALUE'h0`	`RESET_VALUE'h0`


Line 186...	Line 280...
`BITS-10`	`BITS-10`



`update_value`	`update_value`
`wire`	`reg`
`out`	`out`
`BITS-10`	`BITS-10`



Line 202...	Line 296...