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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 253...	Line 253...





`gen_verilogLib_sim`	`gen_verilog`
`105.0`	`104.0`
`none`	`none`
`:Simulation:`	`common`
`./tools/verilog/gen_verilogLib`	`./tools/verilog/gen_verilog`


`dest_dir`	`destination`
`../verilog`	`jtag_tap`


`view`
`sim`






`gen_verilogLib_syn`
`105.0`
`none`
`:Synthesis:`
`./tools/verilog/gen_verilogLib`


`dest_dir`
`../verilog`


`view`
`syn`









Line 311...	Line 289...

`Hierarchical`	`Hierarchical`

`spirit:library="cde"`	`spirit:library="cde"`
`spirit:name="jtag"`	`spirit:name="jtag"`
`spirit:version="def.design"/>`	`spirit:version="tap.design"/>`



	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`






	`commoncommon`
	`Verilog`


	`fs-common`






`sim:Simulation:`	`sim:Simulation:`
`Verilog`	`Verilog`


Line 357...	Line 357...






`INST_LENGTH4`
`INST_RETURN4'b1101`
`INST_RESET4'b1111`
`CHIP_ID_VAL32'h12345678`
`NUM_USER2`
`EXTEST4'b0000`
`USER8'b1010_1001`
`SAMPLE4'b0001`
`HIGHZ_MODE4'b0010`
`CHIP_ID_ACCESS4'b0011`
`CLAMP4'b1000`
`RPC_DATA4'b1010`
`RPC_ADD4'b1001`
`BYPASS4'b1111`










`tap_highz_mode`
`reg`
`out`


`bsr_output_mode`
`reg`
`out`


`bsr_tdo_i`
`wire`
`in`


`jtag_clk`
`wire`
`out`


`update_dr_o`
`reg`
`out`


`bsr_select_o`
`wire`	`fs-common`
`out`






	`../verilog/tap`
	`verilogSourcefragment`












`fs-sim`	`fs-sim`



	`../verilog/copyright`
	`verilogSourceinclude`





`../verilog/jtag_tap`	`../verilog/common/jtag_tap`
`verilogSourcemodule`	`verilogSourcemodule`



`dest_dir`	`dest_dir`
`../verilog/sim/`	`../views/sim/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`




Line 453...	Line 417...

`../verilog/SYNTHESYS`	`../verilog/SYNTHESYS`
`verilogSourceinclude`	`verilogSourceinclude`




	`../verilog/copyright`
	`verilogSourceinclude`






`../verilog/jtag_tap`	`../verilog/common/jtag_tap`
`verilogSourcemodule`	`verilogSourcemodule`




`dest_dir`	`dest_dir`
`../verilog/syn/`	`../views/syn/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`




Line 478...	Line 447...


`fs-lint`	`fs-lint`

`dest_dir`	`dest_dir`
`../verilog/syn/`	`../views/syn/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`












	`INST_LENGTH4`
	`INST_RETURN4'b1101`
	`INST_RESET4'b1111`
	`CHIP_ID_VAL32'h00000000`
	`NUM_USER2`
	`EXTEST4'b0000`
	`USER8'b1010_1001`
	`SAMPLE4'b0001`
	`HIGHZ_MODE4'b0010`
	`CHIP_ID_ACCESS4'b0011`
	`CLAMP4'b1000`
	`RPC_DATA4'b1010`
	`RPC_ADD4'b1001`
	`BYPASS4'b1111`










	`tap_highz_mode`
	`reg`
	`out`


	`bsr_output_mode`
	`reg`
	`out`


	`bsr_tdo_i`
	`wire`
	`in`


	`jtag_clk`
	`wire`
	`out`


	`update_dr_o`
	`reg`
	`out`


	`bsr_select_o`
	`wire`
	`out`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.xml] - Diff between revs 133 and 134