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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [lifo/] [rtl/] [xml/] [cde_lifo_def.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 17...	Line 17...






	`gen_verilog`
	`104.0`
	`none`
	`common`
	`./tools/verilog/gen_verilog`


	`destination`
	`lifo_def`













`fs-sim`



`dest_dir`
`../verilog/`
`verilogSourcelibraryDir`






`fs-syn`


`dest_dir`
`../verilog/`
`verilogSourcelibraryDir`









`fs-lint`

`dest_dir`
`../verilog/`
`verilogSourcelibraryDir`

















Line 87...	Line 52...
`spirit:library="cde"`	`spirit:library="cde"`
`spirit:name="lifo"`	`spirit:name="lifo"`
`spirit:version="def.design"/>`	`spirit:version="def.design"/>`



	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`







	`commoncommon`
	`Verilog`


	`fs-common`








`sim:Simulation:`	`sim:Simulation:`

Line 128...	Line 117...














	`fs-common`



	`../verilog/lifo_def`
	`verilogSourcefragment`





	`../verilog/copyright`
	`verilogSourceinclude`











	`fs-sim`



	`../verilog/common/lifo_def`
	`verilogSourcemodule`





	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`






	`fs-syn`


	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`









	`fs-lint`

	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`















`WIDTH8`	`WIDTH8`
`SIZE2`	`SIZE2`
`WORDS4`	`WORDS4`
`WRITETHRU0`	`WRITETHRU1`
`DEFAULT8'hff`





Line 170...	Line 246...
`WIDTH-10`	`WIDTH-10`



`dout`	`dout`
`reg`	`wire`
`out`	`out`
`WIDTH-10`	`WIDTH-10`

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