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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [verilog/] [top.generic] - Diff between revs 131 and 135

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Rev 131	Rev 135
Line 18...	Line 18...

`wire [2*WIDTH-1:0] mul_prod;`	`wire [2*WIDTH-1:0] mul_prod;`
`reg [1:0] mul_stall_count;`	`reg [1:0] mul_stall_count;`


`ifndef SYNTHESYS	`ifndef SYNTHESIS

`always@(posedge clk)`	`always@(posedge clk)`

`if(mul_stall_count == 2'b10)`	`if(mul_stall_count == 2'b10)`
`begin`	`begin`

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