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https://opencores.org/ocsvn/socgen/socgen/trunk
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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cde
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cde
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mult
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mult
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ord_r4 default
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ord_r4
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gen_verilog
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gen_verilog
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104.0
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104.0
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none
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none
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common
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:*common:*
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./tools/verilog/gen_verilog
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tools/verilog/gen_verilog
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destination
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destination
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mult_ord_r4
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mult_ord_r4
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gen_verilogLib_sim
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gen_verilogLib_sim
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105.0
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105.0
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none
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none
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:*Simulation:*
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:*Simulation:*
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./tools/verilog/gen_verilogLib
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tools/verilog/gen_verilogLib
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dest_dir
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dest_dir
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../views
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../views
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view
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view
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sim
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sim
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gen_verilogLib_syn
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gen_verilogLib_syn
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105.0
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105.0
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none
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none
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:*Synthesis:*
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:*Synthesis:*
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./tools/verilog/gen_verilogLib
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tools/verilog/gen_verilogLib
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dest_dir
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dest_dir
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../views
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../views
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view
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view
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syn
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syn
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fs-common
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../verilog/top.ord_r4
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verilogSourcefragment
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fs-sim
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../verilog/common/mult_ord_r4
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verilogSourcemodule
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verilog
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verilog
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cde_mult_ord_r4
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WIDTH
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16
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fs-sim
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../verilog/ord_r4.v
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verilogSourcemodule
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dest_dir../views/sim/
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verilogSourcelibraryDir
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fs-syn
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rtl
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verilog:Kactus2:
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verilog
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../verilog/common/mult_ord_r4
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verilogSourcemodule
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../verilog/ord_r4.v
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verilogSourcemodule
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common:*common:*
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Verilog
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dest_dir../views/syn/
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verilogSourcelibraryDir
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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fs-lint
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Verilog
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dest_dir../views/syn/
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verilogSourcelibraryDir
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fs-syn
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doc
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="documentation"/>
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:*Documentation:*
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Verilog
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WIDTH16
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commoncommon
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Verilog
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clk
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wire
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in
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fs-common
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reset
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wire
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in
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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a_in
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wire
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in
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fs-syn
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WIDTH-10
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b_in
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doc
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wire
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in
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WIDTH-10
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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alu_op_mul
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wire
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in
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ex_freeze
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wire
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in
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mul_prod_r
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reg
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out
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2*WIDTH-10
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mul_stall
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wire
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out
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clk
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wire
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in
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reset
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wire
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in
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a_in
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wire
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in
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WIDTH-10
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b_in
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wire
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fs-common
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in
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WIDTH-10
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alu_op_mul
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wire
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../verilog/top.ord_r4
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in
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verilogSourcefragment
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ex_freeze
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wire
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fs-sim
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in
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../verilog/common/mult_ord_r4
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verilogSourcemodule
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../verilog/ord_r4.v
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verilogSourcemodule
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mul_prod_r
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reg
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out
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2*WIDTH-10
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mul_stall
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wire
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dest_dir../views/sim/
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out
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verilogSourcelibraryDir
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fs-syn
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../verilog/common/mult_ord_r4
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verilogSourcemodule
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../verilog/ord_r4.v
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verilogSourcemodule
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dest_dir../views/syn/
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verilogSourcelibraryDir
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fs-lint
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dest_dir../views/syn/
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verilogSourcelibraryDir
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