URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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Rev 135 |
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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cde
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cde
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pad
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pad
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se_dig default
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se_dig
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pad_ring
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pad_ring
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PAD_io
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PAD
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PAD_io
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PAD
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pad
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pad
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pad_out
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pad_out
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pad_oe
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pad_oe
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pad_in
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pad_in
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pad_out
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pad_out
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pad_oe
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pad_oe
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pad_in
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pad_in
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gen_verilog
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gen_verilog
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104.0
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104.0
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none
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none
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common
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:*common:*
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./tools/verilog/gen_verilog
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tools/verilog/gen_verilog
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destination
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destination
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pad_se_dig
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pad_se_dig
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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commoncommon
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Verilog
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verilog
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verilog
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cde_pad_se_dig
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fs-common
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WIDTH
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1
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OE_WIDTH
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1
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sim:*Simulation:*
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Verilog
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fs-sim
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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doc
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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rtl
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verilog:Kactus2:
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verilog
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verilog
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="verilog"/>
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WIDTH1
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common:*common:*
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Verilog
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fs-common
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PAD
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wire
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sim:*Simulation:*
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inout
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Verilog
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WIDTH-10
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fs-sim
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pad_in
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wire
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syn:*Synthesis:*
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out
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Verilog
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WIDTH-10
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fs-syn
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pad_out
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wire
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in
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WIDTH-10
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pad_oe
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wire
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doc
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in
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="documentation"/>
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:*Documentation:*
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Verilog
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WIDTH1
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OE_WIDTH1
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PAD
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wire
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inout
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WIDTH-10
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pad_in
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wire
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out
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WIDTH-10
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pad_out
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wire
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in
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WIDTH-10
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pad_oe
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wire
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in
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OE_WIDTH-10
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fs-common
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../verilog/pad_se_dig
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verilogSourcefragment
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fs-sim
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fs-common
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../verilog/copyright
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verilogSourceinclude
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../verilog/pad_se_dig
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verilogSourcefragment
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../verilog/common/pad_se_dig
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verilogSourcemodule
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dest_dir
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../views/sim/
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verilogSourcelibraryDir
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fs-syn
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fs-sim
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../verilog/copyright
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../verilog/copyright
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verilogSourceinclude
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verilogSourceinclude
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../verilog/common/pad_se_dig
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../verilog/common/pad_se_dig
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verilogSourcemodule
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verilogSourcemodule
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dest_dir
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../views/syn/
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verilogSourcelibraryDir
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dest_dir
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../views/sim/
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verilogSourcelibraryDir
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fs-lint
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fs-syn
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dest_dir
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../views/syn/
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verilogSourcelibraryDir
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../verilog/copyright
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verilogSourceinclude
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../verilog/common/pad_se_dig
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verilogSourcemodule
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dest_dir
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../views/syn/
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verilogSourcelibraryDir
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fs-lint
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dest_dir
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../views/syn/
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verilogSourcelibraryDir
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refdes
|
|
P?
|
|
800
|
|
1000
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5
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|
10
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1
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1
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|
2
|
|
|
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|
module_name
|
|
cde_pad_se_dig
|
|
400
|
|
0
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5
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|
10
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0
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|
1
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2
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|
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|
|
vendor
|
|
opencores.org
|
|
0
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|
-200
|
|
0
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|
10
|
|
0
|
|
0
|
|
0
|
|
|
|
|
|
|
|
library
|
|
cde
|
|
0
|
|
-300
|
|
0
|
|
10
|
|
0
|
|
0
|
|
0
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|
|
|
|
|
|
|
|
|
component
|
|
pad
|
|
0
|
|
-400
|
|
0
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10
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0
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|
0
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0
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version
|
|
se_dig
|
|
0
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|
-500
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0
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10
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0
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0
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0
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cde_pad_se_dig
|
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|
geda-project.org
|
|
symbols
|
|
pads
|
|
def
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|
io_pad
|
|
100
|
|
00
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|
geda-project.org
|
|
symbols
|
|
pads
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def
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|
oe_wire
|
|
0
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|
600
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|
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|
geda-project.org
|
|
symbols
|
|
pins
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def
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|
out_wire
|
|
1300
|
|
600
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|
PAD
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0
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|
geda-project.org
|
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symbols
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|
pins
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def
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in_wire
|
|
0
|
|
900
|
|
pad_oe
|
|
0
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|
geda-project.org
|
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symbols
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|
pins
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def
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in_wire
|
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0
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|
600
|
|
pad_out
|
|
0
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|
geda-project.org
|
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symbols
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pins
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def
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out_wire_m
|
|
000
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|
200
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pad_in
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0
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vector
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|
geda-project.org
|
|
symbols
|
|
pads
|
|
def
|
|
io_pad
|
|
100
|
|
00
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|
|
|
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|
geda-project.org
|
|
symbols
|
|
pads
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|
def
|
|
oe_bus
|
|
0
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|
600
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geda-project.org
|
|
symbols
|
|
pins
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def
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out_bus
|
|
1300
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|
600
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PAD
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0
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geda-project.org
|
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symbols
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|
pins
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|
def
|
|
in_bus
|
|
0
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|
900
|
|
pad_oe
|
|
0
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|
geda-project.org
|
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symbols
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|
pins
|
|
def
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|
in_bus
|
|
0
|
|
600
|
|
pad_out
|
|
0
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|
|
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geda-project.org
|
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symbols
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|
pins
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|
def
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|
out_bus_m
|
|
000
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|
200
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pad_in
|
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0
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scmd
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geda-project.org
|
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symbols
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pads
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def
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|
io_pad
|
|
100
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|
00
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geda-project.org
|
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symbols
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|
pads
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def
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|
oe_wire
|
|
0
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600
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geda-project.org
|
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symbols
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pins
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def
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out_bus
|
|
1300
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600
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PAD
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0
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|
geda-project.org
|
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symbols
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|
pins
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def
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in_wire
|
|
0
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|
900
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pad_oe
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0
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geda-project.org
|
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symbols
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pins
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def
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in_bus
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0
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600
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pad_out
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0
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geda-project.org
|
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symbols
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pins
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def
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out_bus_m
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000
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200
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pad_in
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0
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