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     <p style="margin-bottom: 0in;"><a href="#cde_sram_def">cde_sram_def<br>
 
<H1><A NAME="Datasheet"></A>SOCGEN Datasheet:</H1>
 
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 <br>  Synchronous one-port ram
 
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                        <LI><P STYLE="margin-bottom: 0in"><A HREF="#TheoryofOperation">Theory
 
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<H2 CLASS="western"><A NAME="TheoryofOperation"></A><B>Theory of
 
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Operation</B></H2>
 
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<P>The synchronous ram modules provide a variety of memory storage
 
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options. <BR>Both reads and writes are synchronous to the rising edge
 
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of clk. <BR>Memory may be initialized from a bit file and later
 
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overwritten by memory writes. <BR>If WRITETHRU is set to 1 then a
 
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simultaneous read/write to the same address will read the new data.
 
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<BR>If set to 0 it will return the old.
 
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