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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_byte.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 14...	Line 14...
`sram`	`sram`
`byte default`	`byte default`








	`gen_verilog`
	`104.0`
	`none`
	`common`
	`./tools/verilog/gen_verilog`


	`destination`
	`sram_byte`




















	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`




	`commoncommon`
	`Verilog`


	`fs-common`






`sim:Simulation:`	`sim:Simulation:`

`Verilog`	`Verilog`
Line 76...	Line 121...







`ADDR0`
`WORDS0`
`WRITETHRU0`
`DEFAULT{8'bxxxxxxxx}`




`clk`	`clk`
`wire`	`wire`
`in`	`in`
Line 144...	Line 181...






	`fs-common`






	`../verilog/sram_byte`
	`verilogSourcefragment`






`fs-sim`	`fs-sim`


`dest_dir../verilog/`
	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/common/sram_byte`
	`verilogSourcemodule`





	`dest_dir../views/sim/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`






`fs-syn`	`fs-syn`




	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/common/sram_byte`
	`verilogSourcemodule`







`dest_dir../verilog/`	`dest_dir../views/syn/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`




Line 175...	Line 256...

`fs-lint`	`fs-lint`



`dest_dir../verilog/lint/`	`dest_dir../views/syn/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`

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