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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Diff between revs 131 and 134

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Rev 131	Rev 134
Line 14...	Line 14...
`sram`	`sram`
`dp default`	`dp default`






	`gen_verilog`
	`104.0`
	`none`
	`common`
	`./tools/verilog/gen_verilog`


	`destination`
	`sram_dp`

















	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`




	`commoncommon`
	`Verilog`


	`fs-common`





`sim:Simulation:`	`sim:Simulation:`
`Verilog`	`Verilog`

`fs-sim`	`fs-sim`

Line 69...	Line 108...







`ADDR0`
`WIDTH0`
`WORDS0`
`WRITETHRU0`
`DEFAULT{WIDTH{1'bx}}`







`clk`	`clk`
`wire`	`wire`
Line 142...	Line 170...






	`fs-common`



	`../verilog/sram_dp`
	`verilogSourcefragment`



`fs-sim`


`dest_dir../verilog/`
`verilogSourcelibraryDir`	`../verilog/copyright`
	`verilogSourceinclude`








`fs-syn`	`fs-sim`




`dest_dir../verilog/`
`verilogSourcelibraryDir`	`../verilog/common/sram_dp`
	`verilogSourcemodule`




	`dest_dir../views/sim/`
	`verilogSourcelibraryDir`








`fs-lint`	`fs-syn`




`dest_dir../verilog/lint/`
`verilogSourcelibraryDir`	`../verilog/common/sram_dp`
	`verilogSourcemodule`






	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`








	`fs-lint`


	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`

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