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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_word.xml] - Diff between revs 131 and 134

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Rev 131	Rev 134
Line 106...	Line 106...









	`gen_verilog`
	`104.0`
	`none`
	`common`
	`./tools/verilog/gen_verilog`


	`destination`
	`sram_word`














	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`




	`commoncommon`
	`Verilog`


	`fs-common`






`sim:Simulation:`	`sim:Simulation:`
`Verilog`	`Verilog`


`fs-sim`	`fs-sim`
Line 160...	Line 204...






`ADDR0`
`WORDS0`
`WRITETHRU0`
`DEFAULT{WIDTH{1'bx}}`






`cs`	`cs`
Line 179...	Line 216...


`addr`	`addr`
`wire`	`wire`
`in`	`in`
`ADDR-10`	`ADDR1`



`wdata`	`wdata`
`wire`	`wire`
Line 216...	Line 253...






	`fs-common`



	`../verilog/sram_word`
	`verilogSourcefragment`










`fs-sim`	`fs-sim`




	`../verilog/copyright`
	`verilogSourceinclude`




`dest_dir../verilog/`
	`../verilog/common/sram_word`
	`verilogSourcemodule`




	`dest_dir../views/sim/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`




Line 236...	Line 300...



`fs-syn`	`fs-syn`



	`../verilog/copyright`
	`verilogSourceinclude`






	`../verilog/common/sram_word`
	`verilogSourcemodule`





`dest_dir../verilog/`	`dest_dir../views/syn/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`




Line 255...	Line 333...

`fs-lint`	`fs-lint`



`dest_dir../verilog/lint/`	`dest_dir../views/syn/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`

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