OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_with_reset.xml] - Diff between revs 131 and 134

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Rev 131 Rev 134
Line 12... Line 12...
opencores.org
opencores.org
cde
cde
sync
sync
with_reset  default
with_reset  default
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog
 
  104.0
 
  none
 
  common
 
  ./tools/verilog/gen_verilog
 
  
 
    
 
      destination
 
      sync_with_reset
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   
   
 
 
 
 
       
       
 
              verilog
 
              
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="verilog"/>
 
              
 
              
 
 
 
 
 
 
 
 
 
 
 
 
 
              
 
              commoncommon
 
              Verilog
 
              
 
                     
 
                            fs-common
 
                     
 
              
 
 
 
 
 
 
 
              
 
              sim:*Simulation:*
 
              Verilog
 
              
 
                     
 
                            fs-sim
 
                     
 
              
 
 
 
              
 
              syn:*Synthesis:*
 
              Verilog
 
              
 
                     
 
                            fs-syn
 
                     
 
              
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
       
              doc
              doc
              
              
              
              
                                   spirit:library="Testbench"
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:name="toolflow"
Line 76... Line 155...
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   
 
      fs-common
 
 
 
      
 
        
 
        ../verilog/sync_with_reset
 
        verilogSourcefragment
 
      
 
 
 
 
 
 
 
 
 
 
 
   
 
 
 
 
 
 
   
   
      fs-sim
      fs-sim
 
 
 
 
      
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
 
 
      
 
        
 
        ../verilog/common/sync_with_reset
 
        verilogSourcemodule
 
      
 
 
 
      
      dest_dir
      dest_dir
        ../verilog/
        ../views/sim/
        verilogSource
        verilogSource
        libraryDir
        libraryDir
      
      
 
 
  
  
Line 94... Line 205...
 
 
   
   
      fs-syn
      fs-syn
 
 
      
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
 
 
      
 
        
 
        ../verilog/common/sync_with_reset
 
        verilogSourcemodule
 
      
 
 
 
 
 
      
dest_dir
dest_dir
        ../verilog/
        ../views/syn/
        verilogSource
        verilogSource
        libraryDir
        libraryDir
      
      
 
 
 
 
Line 110... Line 235...
   
   
      fs-lint
      fs-lint
 
 
      
      
      dest_dir
      dest_dir
        ../verilog/
        ../views/syn/
        verilogSource
        verilogSource
        libraryDir
        libraryDir
      
      
 
 
   
   

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