| Line 1... |
Line 1... |
v 20100214 2
|
v 20110115 2
|
C 42500 22100 1 0 0 frame_800x600.sym
|
C 42300 22200 1 0 0 frame_800x600.sym
|
B 42900 27700 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
T 43200 27900 9 10 1 0 0 0 1
|
B 42900 26100 1000 1900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
T 43000 27200 9 10 1 0 0 0 1
|
|
LIB
|
|
T 43000 26900 9 10 1 0 0 0 1
|
|
BENCH
|
|
T 43000 27800 9 10 1 0 0 0 1
|
|
DOC
|
|
T 43000 26600 9 10 1 0 0 0 1
|
|
TARGETS
|
|
T 43000 27500 9 10 1 0 0 0 1
|
|
TOOLS
|
TOOLS
|
T 43900 25900 9 10 1 0 0 0 1
|
T 42600 28300 9 20 1 0 0 0 1
|
Proj #1
|
Socgen
|
T 44500 25600 9 10 1 0 0 0 1
|
T 43200 27100 9 10 1 0 0 0 1
|
CMP #1
|
|
B 42900 26800 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
B 42900 26500 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
B 42900 27400 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
B 42900 27100 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
B 42900 24600 2300 1500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
B 44400 25500 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
T 46300 27900 9 20 1 0 0 0 1
|
|
Socgen Design Environment
|
|
T 42900 26200 9 10 1 0 0 0 1
|
|
PROJECTS
|
PROJECTS
|
B 44400 25200 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
T 43200 24100 9 10 1 0 0 0 1
|
T 44500 25300 9 10 1 0 0 0 1
|
|
CMP #2
|
|
B 44400 24900 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
T 44500 25000 9 10 1 0 0 0 1
|
|
CMP #3
|
|
B 44400 24600 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
T 44500 24700 9 10 1 0 0 0 1
|
|
CMP #4
|
|
B 42900 23400 2300 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
B 44400 24000 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
B 44400 23700 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
B 44400 23400 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
T 43900 24400 9 10 1 0 0 0 1
|
|
Proj #2
|
|
T 44500 24100 9 10 1 0 0 0 1
|
|
CMP #1
|
|
T 44500 23800 9 10 1 0 0 0 1
|
|
CMP #2
|
|
T 44500 23500 9 10 1 0 0 0 1
|
|
CMP #3
|
|
B 42900 22500 2300 900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
B 44400 22800 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
B 44400 22500 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
T 43900 23200 9 10 1 0 0 0 1
|
|
Proj #3
|
|
T 44500 22900 9 10 1 0 0 0 1
|
|
CMP #1
|
|
T 44500 22600 9 10 1 0 0 0 1
|
|
CMP #2
|
|
B 43900 26500 1300 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
T 44000 26600 9 10 1 0 0 0 1
|
|
TARGET #1
|
|
B 45200 26500 1300 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
T 45300 26600 9 10 1 0 0 0 1
|
|
TARGET #2
|
|
B 46500 26500 1300 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
T 46600 26600 9 10 1 0 0 0 1
|
|
TARGET #3
|
|
B 47800 26500 1300 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
T 47900 26600 9 10 1 0 0 0 1
|
|
TARGET #4
|
|
B 42900 22200 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
T 43000 22300 9 10 1 0 0 0 1
|
|
WORK
|
WORK
|
|
L 43100 28300 43100 24100 3 0 0 0 -1 -1
|
|
T 43700 26900 9 10 1 0 0 0 1
|
|
opencores.org
|
|
T 43700 25000 9 10 1 0 0 0 1
|
|
accellera.org
|
|
T 43700 24800 9 10 1 0 0 0 1
|
|
vendor_1
|
|
T 43700 24500 9 10 1 0 0 0 1
|
|
vendor_2
|
|
T 44200 26700 9 10 1 0 0 0 1
|
|
lib_1
|
|
T 44200 26500 9 10 1 0 0 0 1
|
|
lib_2
|
|
T 43700 27700 9 10 1 0 0 0 1
|
|
install
|
|
T 43700 27500 9 10 1 0 0 0 1
|
|
bin
|
|
T 43200 23600 9 10 1 0 0 0 1
|
|
Makefile
|
|
L 43100 27900 43800 27900 3 0 0 0 -1 -1
|
|
L 43100 27100 44200 27100 3 0 0 0 -1 -1
|
|
L 43100 24100 43800 24100 3 0 0 0 -1 -1
|
|
L 43700 27100 43700 26900 3 0 0 0 -1 -1
|
|
L 43700 26900 44800 26900 3 0 0 0 -1 -1
|
|
L 43600 27900 43600 27500 3 0 0 0 -1 -1
|
|
L 43600 27500 44200 27500 3 0 0 0 -1 -1
|
|
L 43600 27700 44200 27700 3 0 0 0 -1 -1
|
|
L 43700 26900 43700 24500 3 0 0 0 -1 -1
|
|
L 43700 24500 44500 24500 3 0 0 0 -1 -1
|
|
L 43700 24800 44400 24800 3 0 0 0 -1 -1
|
|
L 43700 25000 44800 25000 3 0 0 0 -1 -1
|
|
L 44200 26900 44200 26400 3 0 0 0 -1 -1
|
|
L 44200 26400 44600 26400 3 0 0 0 -1 -1
|
|
L 44200 26700 44600 26700 3 0 0 0 -1 -1
|
|
T 44500 26200 9 10 1 0 0 0 1
|
|
doc
|
|
T 44500 26000 9 10 1 0 0 0 1
|
|
bin
|
|
T 44500 25800 9 10 1 0 0 0 1
|
|
sw
|
|
T 44500 25600 9 10 1 0 0 0 1
|
|
ip
|
