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Subversion Repositories socgen

[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] [data_fig3.sch] - Diff between revs 56 and 81

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Rev 56 Rev 81
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v 20100214 2
 
v 20100214 2
 
C 42600 22000 1 0 0 frame_800x600.sym
 
C 42300 22100 1 0 0 frame_800x600.sym
 
B 49500 27200 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 42800 27000 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 42900 22200 6000 5800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 42800 26700 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
T 49500 27300 9 10 1 0 0 0 1
 
B 42800 26000 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
Serial Uart
 
B 42800 25700 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
T 49500 26700 9 10 1 0 0 0 1
 
B 42800 25400 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
VGA Display
 
T 42600 28400 9 10 1 0 0 0 1
 
T 49600 26200 9 10 1 0 0 0 1
 
COMPONENT Database
 
PS2 Mouse
 
T 42600 28000 9 10 1 0 0 0 1
 
T 49600 25600 9 10 1 0 0 0 1
 
COMPONENT
 
Switches
 
T 42900 27100 9 10 1 0 0 0 1
 
T 49700 25100 9 10 1 0 0 0 1
 
FSM1
 
Leds
 
T 42700 27400 9 10 1 0 0 0 1
 
T 49500 24500 9 10 1 0 0 0 1
 
FSM
 
Push Buttons
 
T 42900 26800 9 10 1 0 0 0 1
 
T 49500 23900 9 10 1 0 0 0 1
 
FSM2
 
7 Seg display
 
T 42900 26100 9 10 1 0 0 0 1
 
T 49500 23100 9 10 1 0 0 0 1
 
top.v
 
I/O connectors
 
T 42700 26400 9 10 1 0 0 0 1
 
B 49500 25500 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
VERILOG
 
B 49500 25000 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
T 42900 25800 9 10 1 0 0 0 1
 
B 49500 26600 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
rtl1.v
 
B 49500 26100 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
T 42900 25500 9 10 1 0 0 0 1
 
B 49500 24400 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
rtl2.v
 
B 49500 23800 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 42800 24600 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 49500 23000 1200 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 42800 24300 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
T 43000 28400 9 10 1 0 0 0 1
 
B 42800 24000 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
System
 
T 42900 24700 9 10 1 0 0 0 1
 
T 43100 27600 9 10 1 0 0 0 1
 
VAR/define.v
 
PCA  (Nexys2)
 
T 42700 25000 9 10 1 0 0 0 1
 
T 43400 26900 9 10 1 0 0 0 1
 
VARIANTS
 
Targeted Component  (Xilinx Spartan 3E-500 FG320)
 
T 42900 24400 9 10 1 0 0 0 1
 
B 43200 22600 5400 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
VAR1/define.v
 
B 43500 23100 4800 3500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
T 42900 24100 9 10 1 0 0 0 1
 
T 43800 26200 9 10 1 0 0 0 1
 
VAR2/define.v
 
Padring
 
T 42500 27700 9 10 1 0 0 0 1
 
T 44100 25700 9 10 1 0 0 0 1
 
RTL
 
Core
 
B 42600 22400 2000 5200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
T 44300 25200 9 10 1 0 0 0 1
 
B 45200 27000 1500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
Component
 
B 45200 24600 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 43800 23500 4200 2500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 45200 24300 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 44100 23800 3600 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 45200 24000 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 44400 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 44900 23900 1900 3700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
B 45500 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
T 45300 27100 9 10 1 0 0 0 1
 
B 46600 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
VAR1_PROG2
 
T 44500 24800 9 10 1 0 0 0 1
 
T 45100 27400 9 10 1 0 0 0 1
 
comp
 
RUN
 
T 45600 24800 9 10 1 0 0 0 1
 
T 45300 26800 9 10 1 0 0 0 1
 
comp
 
VAR2_PROG1
 
T 46700 24800 9 10 1 0 0 0 1
 
T 45300 26500 9 10 1 0 0 0 1
 
comp
 
VAR1_TST1
 
B 44500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
T 45300 26200 9 10 1 0 0 0 1
 
B 45500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
VAR2_TST1
 
B 46500 27400 600 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
T 45300 25900 9 10 1 0 0 0 1
 
B 47500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
VAR_TST2
 
T 44600 27600 9 10 1 0 0 0 1
 
T 45300 24700 9 10 1 0 0 0 1
 
IC
 
VAR
 
T 45600 27600 9 10 1 0 0 0 1
 
T 45100 25000 9 10 1 0 0 0 1
 
IC
 
COV
 
T 46600 27600 9 10 1 0 0 0 1
 
T 45300 24400 9 10 1 0 0 0 1
 
IC
 
VAR1
 
T 47600 27600 9 10 1 0 0 0 1
 
T 45300 24100 9 10 1 0 0 0 1
 
IC
 
VAR2
 
L 48900 27400 49500 27400 3 0 0 0 -1 -1
 
T 44900 27700 9 10 1 0 0 0 1
 
L 48900 26800 49500 26800 3 0 0 0 -1 -1
 
SIM
 
L 48900 26300 49500 26300 3 0 0 0 -1 -1
 
B 45200 26700 1500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
L 48900 25700 49500 25700 3 0 0 0 -1 -1
 
B 45200 26400 1500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
L 48900 25200 49500 25200 3 0 0 0 -1 -1
 
B 45200 26100 1500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
L 48900 24600 49500 24600 3 0 0 0 -1 -1
 
B 45200 25800 1500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
L 48900 24000 49500 24000 3 0 0 0 -1 -1
 
B 47000 23900 2100 3700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
L 48900 23200 49500 23200 3 0 0 0 -1 -1
 
T 47100 27100 9 10 1 0 0 0 1
 
 
 
TRG1_VAR1_PROG2
 
 
 
T 47000 27700 9 10 1 0 0 0 1
 
 
 
SYN
 
 
 
T 47100 26800 9 10 1 0 0 0 1
 
 
 
TRG1_VAR2_PROG2
 
 
 
T 47100 26500 9 10 1 0 0 0 1
 
 
 
TRG1_VAR3_PROG2
 
 
 
T 47100 26200 9 10 1 0 0 0 1
 
 
 
TRG2_VAR1_PROG2
 
 
 
T 47100 25900 9 10 1 0 0 0 1
 
 
 
TRG2_VAR2_PROG1
 
 
 
B 42800 23300 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
 
 
B 42800 23000 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
 
 
B 42800 22700 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
 
 
T 42900 23400 9 10 1 0 0 0 1
 
 
 
VAR.xml
 
 
 
T 42700 23700 9 10 1 0 0 0 1
 
 
 
XML
 
 
 
T 42900 23100 9 10 1 0 0 0 1
 
 
 
VAR1.xml
 
 
 
T 42900 22800 9 10 1 0 0 0 1
 
 
 
VAR2.xml
 
 
 
T 47000 23500 9 10 1 0 0 0 1
 
 
 
DOCS
 
 
 
B 47000 22600 2100 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
 
 
B 44900 22600 1900 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
 
 
T 44800 23500 9 10 1 0 0 0 1
 
 
 
GEN
 
 
 
B 45000 23000 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
 
 
B 45000 22700 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
 
 
T 45100 23100 9 10 1 0 0 0 1
 
 
 
sim/files.v
 
 
 
T 45100 22800 9 10 1 0 0 0 1
 
 
 
syn.files.v
 
 
 
B 47100 27000 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
 
 
B 47100 26700 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
 
 
B 47100 26400 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
 
 
B 47100 26100 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
 
 
 
B 47100 25800 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1

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