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<meta http-equiv="CONTENT-TYPE" content="text/html; charset=utf-8">
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<title>signal,port and pad naming guidelines</title>
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<title>signal,port and pad naming guidelines</title>
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<h1><a name="socgen_project"></a>SOCGEN Project</h1>
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<h1><a name="socgen_project"></a>SOCGEN Project</h1>
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<h2>Signal,Port and Pad Naming Guidelines</h2>
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<h2>Signal,Port and Pad Naming Guidelines</h2>
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<p><br>
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<p><br>
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<br>
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<br>
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</p>
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</p>
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<p>As designs and design teams continue to grow in size it is mandatory
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<p>As Digital designs and design teams continue to grow it is
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that all rtl code must follow established name space guidelines. The
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mandatory
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days when designers could simply pull names out of thin air are faster
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that all rtl code must follow an established name space guideline. The
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days when designers could simply pull names out of thin air are fast
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disappearing. Naming guidelines have three functions. First they
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disappearing. Naming guidelines have three functions. First they
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ensure that no two designers select the same name for different objects
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ensure that no two designers select the same name for different objects
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and have a name collision. The second function is to ensure that the
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and have a name collision. The second function is to ensure that the
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chosen names are meaningful to all of the design team. It is quite
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chosen names are meaningful to all of the design team. It is quite
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common for designers to select names
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common for designers to select names
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<p><br>
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<p><br>
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There are two distinct groups that use these names. The IC design team
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There are two distinct groups that use these names. The IC design team
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is one group and it will use all three. The other group consists
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is one group and it will use all three. The other group consists
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of System designers,PCB designers, Board Test engineers etc.<br>
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of System designers,PCB designers, Board Test engineers etc.<br>
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They only access the chip via the pad names and never see the internal
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They only access the chip via the pad names and never see the internal
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ones. These two groups have incompatible objectives. The IC
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ones. These two groups often have incompatible objectives. The IC
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design team is dealing with millions of names and needs a naming scheme
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design team is dealing with millions of names and needs a naming scheme
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that produces long descriptive names that won't collide and conveys
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that produces long descriptive names that won't collide and conveys
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information about the signals function. <br>
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information about the signals function. <br>
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</p>
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</p>
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<p>The rest of the world is only dealing with a few hundred or thousand
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<p>The rest of the world is only dealing with a few hundred or thousand
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names. They also have their own naming requirements. These typically
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names. They also have their own naming requirements as well. These
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typically
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are:<br>
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are:<br>
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</p>
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</p>
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<p><br>
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<p><br>
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</p>
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</p>
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<ul>
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<ul>
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wasted white space on your schematic.</li>
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wasted white space on your schematic.</li>
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</ul>
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</ul>
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<br>
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<br>
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<ul>
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<ul>
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<li>Capital Letters. They make a packed schematic
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<li>Capital Letters. They make a packed schematic
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readable. You don't want your board designers trying to guess if it's a
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readable. You don't want your board designers squinting at a sheet
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trying to guess if it's a
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1 or a l.</li>
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1 or a l.</li>
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</ul>
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</ul>
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<br>
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<br>
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<ul>
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<ul>
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<li>ATE naming requirements. Do you know what the IEEE 1149.1
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<li>ATE naming requirements. Do you know what the IEEE 1149.1
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pad naming rules are? If not then you shouldn't be selecting pad names.</li>
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pad naming rules are? If not then you better not try to pick any pad
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names.</li>
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</ul>
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</ul>
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<br>
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<br>
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<br>
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<br>
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The guideline for selecting pad names is that the IC design team should
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The guideline for selecting pad names is that the IC design team should
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not attempt to pick pad names based on the internal signal names.
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not attempt to pick pad names based on the internal signal names.
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collisions are avoided by ensuring that ALL pad names start with a
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collisions are avoided by ensuring that ALL pad names start with a
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capital letter and that all internal names start with a small
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capital letter and that all internal names start with a small
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one. <br>
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one. <br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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For internal signal and port names you must first find the four pieces
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For internal signal and port names you must first find the four pieces
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of information that will uniquely identify every signal in the design.
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of information that will uniquely identify every signal in the design.
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These are:<br>
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These are:<br>
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<br>
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<br>
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<br>
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<br>
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</li>
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</li>
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</ul>
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</ul>
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<br>
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<br>
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<br>
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<br>
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<ul>
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<ul>
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<li>ad
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<li>Ad
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hoc
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hoc
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If a signal is not defined by a standard interface then an ad hoc
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If
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a signal is not defined by a standard interface then an ad hoc
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signal can be created based on the designers insight. If a module has 2
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signal can be created based on the designers insight. If a module has 2
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or more signals with the same standard interface then a ad hoc field is
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or more signals with the same standard interface then a ad hoc field is
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needed to distinguish between them.</li>
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needed to distinguish between them.</li>
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</ul>
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</ul>
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<br>
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<br>
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will be one and only one driver per node.</li>
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will be one and only one driver per node.</li>
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</ul>
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</ul>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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You can create signal names by simply gathering this information and
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You can create signal names by simply gathering akk this information
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concatenating it into a name but it is perfectly acceptable to
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and
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drop any field(s) if they are not needed to uniquely identify a node.<br>
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concatenating it into a valid signal name. While you can use all
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For example a IC design may have a signal named "clk". Clk is the
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four fields,it is acceptable to
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drop any field(s) if they are not needed to <br>
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uniquely identify a node. For example a IC design may have a signal
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named "clk". Clk is the
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standard interface name for a clock signal so we know that it is a
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standard interface name for a clock signal so we know that it is a
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clock. The clock interface has two sub_members - rising edge and
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clock. The clock interface has two sub_members - rising edge and
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falling edge. If you have N sub_members then you only have to
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falling edge. If you have N sub_members then you only have to
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identify N-1 of them. In this case the standard chooses _n for falling
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identify N-1 of them. In this case the standard chooses _n for falling
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edge clocks and nothing for rising edge. clk is a rising edge clock. An
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edge clocks and nothing for rising edge. clk is a rising edge clock. An
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<p>It would parse as both a clock signal and a sram signal. If this
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<p>It would parse as both a clock signal and a sram signal. If this
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were a dual port sram then the signal would be:</p>
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were a dual port sram then the signal would be:</p>
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<p><br>
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<p><br>
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</p>
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</p>
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<p>
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<p>
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bank_2_eth_3_sram_a_clk <br>
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bank_2_eth_3_sram_a_clk
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<br>
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</p>
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</p>
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<p><br>
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<p><br>
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</p>
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</p>
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<p>Notice that there is an ad hoc field both before and after the sram
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<p>Notice that there is an ad hoc field both before and after the sram
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interface name and it still parses as both a clock and a sram signal.<br>
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interface name and it still parses as both a clock and a sram signal.<br>
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</p>
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</p>
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<p><br>
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<p><br>
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</p>
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</p>
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<p><br>
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<p><br>
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</p>
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</p>
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<h3 class="western">Clock <br>
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</h3>
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<h3 class="western">Clock <br></h3>
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<p><br>
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<p><br>
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A clock is a signal that drives the clock port of a flipflop.<br>
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A clock is a signal that drives the clock port of a flipflop.<br>
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</p>
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</p>
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<br>
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<br>
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<table style="text-align: left; width: 500px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
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<table style="text-align: left; width: 500px; height: 120px;" border="8"
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cellpadding="4" cellspacing="4">
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<tbody>
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<tbody>
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<tr>
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<tr>
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<td style="vertical-align: top;">Interface<br> </td>
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<td style="vertical-align: top;">Interface<br>
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<td style="vertical-align: top;">Clock<br> </td>
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</td>
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<td style="vertical-align: top;">Name<br> </td>
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<td style="vertical-align: top;">Clock<br>
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<td style="vertical-align: top;">Sub <br> </td>
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</td>
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</tr>
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<td style="vertical-align: top;">Name<br>
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<tr>
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</td>
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<td style="vertical-align: top;"> <br> </td>
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<td style="vertical-align: top;">Sub <br>
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<td style="vertical-align: top;"> <br> </td>
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</td>
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<td style="vertical-align: top;">CLK<br> </td>
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</tr>
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<td style="vertical-align: top;"> <br> </td>
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<tr>
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</tr>
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<td style="vertical-align: top;"> <br>
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<tr>
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</td>
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<td style="vertical-align: top;"> <br> </td>
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<td style="vertical-align: top;"> <br>
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<td style="vertical-align: top;">Rising Edge<br> </td>
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</td>
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<td style="vertical-align: top;">CLK<br> </td>
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<td style="vertical-align: top;">CLK<br>
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<td style="vertical-align: top;"> <br> </td>
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</td>
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</tr>
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<td style="vertical-align: top;"> <br>
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<tr>
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</td>
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<td style="vertical-align: top;"><br> </td>
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</tr>
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<td style="vertical-align: top;">Falling Edge<br> </td>
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<tr>
|
<td style="vertical-align: top;">CLK<br> </td>
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<td style="vertical-align: top;"> <br>
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<td style="vertical-align: top;">_N<br> </td>
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</td>
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<td style="vertical-align: top;">Rising Edge<br>
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</td>
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<td style="vertical-align: top;">CLK<br>
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</td>
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<td style="vertical-align: top;"> <br>
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</td>
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</tr>
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<tr>
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<td style="vertical-align: top;"><br>
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</td>
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<td style="vertical-align: top;">Falling Edge<br>
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</td>
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<td style="vertical-align: top;">CLK<br>
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</td>
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<td style="vertical-align: top;">_N<br>
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</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<h3 class="western">Reset <br>
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</h3>
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<h3 class="western">Reset <br></h3>
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<p><br>
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<p><br>
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A reset is a signal forces nodes into a known safe state<br>
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A reset is a signal forces nodes into a known safe state<br>
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</p>
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</p>
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<br>
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<br>
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<table style="text-align: left; width: 500px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
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<table style="text-align: left; width: 500px; height: 120px;" border="8"
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cellpadding="4" cellspacing="4">
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<tbody>
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<tbody>
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<tr>
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<tr>
|
<td style="vertical-align: top;">Interface<br> </td>
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<td style="vertical-align: top;">Interface<br>
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<td style="vertical-align: top;">Reset<br> </td>
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</td>
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<td style="vertical-align: top;">Name<br> </td>
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<td style="vertical-align: top;">Reset<br>
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<td style="vertical-align: top;">Sub <br> </td>
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</td>
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</tr>
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<td style="vertical-align: top;">Name<br>
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<tr>
|
</td>
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<td style="vertical-align: top;"> <br> </td>
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<td style="vertical-align: top;">Sub <br>
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<td style="vertical-align: top;"> <br> </td>
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</td>
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<td style="vertical-align: top;">RESET<br> </td>
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</tr>
|
<td style="vertical-align: top;"> <br> </td>
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<tr>
|
</tr>
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<td style="vertical-align: top;"> <br>
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<tr>
|
</td>
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<td style="vertical-align: top;"> <br> </td>
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<td style="vertical-align: top;"> <br>
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<td style="vertical-align: top;">Active high sync<br> </td>
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</td>
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<td style="vertical-align: top;">RESET<br> </td>
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<td style="vertical-align: top;">RESET<br>
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<td style="vertical-align: top;"> <br> </td>
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</td>
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</tr>
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<td style="vertical-align: top;"> <br>
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<tr>
|
</td>
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<td style="vertical-align: top;"><br> </td>
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</tr>
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<td style="vertical-align: top;">Active Low async<br> </td>
|
<tr>
|
<td style="vertical-align: top;">RESET<br> </td>
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<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">_N<br> </td>
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</td>
|
|
<td style="vertical-align: top;">Active high sync<br>
|
|
</td>
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<td style="vertical-align: top;">RESET<br>
|
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</td>
|
|
<td style="vertical-align: top;"> <br>
|
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</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
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|
</td>
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<td style="vertical-align: top;">Active Low async<br>
|
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</td>
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<td style="vertical-align: top;">RESET<br>
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</td>
|
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<td style="vertical-align: top;">_N<br>
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|
</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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|
<h3 class="western">Pads <br>
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</h3>
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|
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<h3 class="western">Pads <br></h3>
|
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<p><br>
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<p><br>
|
Pads are the connections made between the pad_ring and the core.<br>
|
Pads are the connections made between the pad_ring and the core.<br>
|
</p>
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</p>
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<br>
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<br>
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<table style="text-align: left; width: 500px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
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<table style="text-align: left; width: 500px; height: 120px;" border="8"
|
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cellpadding="4" cellspacing="4">
|
<tbody>
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<tbody>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;">Interface<br> </td>
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<td style="vertical-align: top;">Interface<br>
|
<td style="vertical-align: top;">Pads<br> </td>
|
</td>
|
<td style="vertical-align: top;">Name<br> </td>
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<td style="vertical-align: top;">Pads<br>
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<td style="vertical-align: top;">Sub <br> </td>
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</td>
|
</tr>
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<td style="vertical-align: top;">Name<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;">Sub <br>
|
<td style="vertical-align: top;"> <br> </td>
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</td>
|
<td style="vertical-align: top;">PAD<br> </td>
|
</tr>
|
<td style="vertical-align: top;"> <br> </td>
|
<tr>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">output<br> </td>
|
</td>
|
<td style="vertical-align: top;">PAD<br> </td>
|
<td style="vertical-align: top;">PAD<br>
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<td style="vertical-align: top;">_OUT <br> </td>
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</td>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
</tr>
|
<td style="vertical-align: top;">Input<br> </td>
|
<tr>
|
<td style="vertical-align: top;">PAD<br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">_IN<br> </td>
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</td>
|
</tr>
|
<td style="vertical-align: top;">output<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;">PAD<br>
|
<td style="vertical-align: top;">Enable<br> </td>
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</td>
|
<td style="vertical-align: top;">PAD<br> </td>
|
<td style="vertical-align: top;">_OUT <br>
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<td style="vertical-align: top;">_OE<br> </td>
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</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Input<br>
|
|
</td>
|
|
<td style="vertical-align: top;">PAD<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_IN<br>
|
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</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Enable<br>
|
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</td>
|
|
<td style="vertical-align: top;">PAD<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_OE<br>
|
|
</td>
|
</tr>
|
</tr>
|
</tbody>
|
</tbody>
|
</table>
|
</table>
|
<br>
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<br>
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<br>
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<br>
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<br>
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<br>
|
|
<h3 class="western">Sram <br>
|
|
</h3>
|
|
|
<h3 class="western">Sram <br></h3>
|
|
<p><br>
|
<p><br>
|
Sram signals connect between the core and an instantiated memory cell.<br>
|
Sram signals connect between the core and an instantiated memory cell.<br>
|
</p>
|
</p>
|
<br>
|
<br>
|
<table style="text-align: left; width: 500px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
|
<table style="text-align: left; width: 500px; height: 120px;" border="8"
|
|
cellpadding="4" cellspacing="4">
|
<tbody>
|
<tbody>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;">Interface<br> </td>
|
<td style="vertical-align: top;">Interface<br>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
</td>
|
<td style="vertical-align: top;">Name<br> </td>
|
<td style="vertical-align: top;">SRAM<br>
|
<td style="vertical-align: top;">Sub <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">Name<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;">Sub <br>
|
<td style="vertical-align: top;"> <br> </td>
|
</td>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
</tr>
|
<td style="vertical-align: top;"> <br> </td>
|
<tr>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">RW Address<br> </td>
|
</td>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
<td style="vertical-align: top;">SRAM<br>
|
<td style="vertical-align: top;">_ADDR <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
</tr>
|
<td style="vertical-align: top;">Read Address<br> </td>
|
<tr>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">_RADDR <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">RW Address<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;">SRAM<br>
|
<td style="vertical-align: top;">Write Address<br> </td>
|
</td>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
<td style="vertical-align: top;">_ADDR <br>
|
<td style="vertical-align: top;">_WADDR <br> </td>
|
</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">Write Data<br> </td>
|
</td>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
<td style="vertical-align: top;">Read Address<br>
|
<td style="vertical-align: top;">_WDATA<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">SRAM<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;">_RADDR <br>
|
<td style="vertical-align: top;">Read Data<br> </td>
|
</td>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
</tr>
|
<td style="vertical-align: top;">_RDATA<br> </td>
|
<tr>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
|
</td>
|
|
<td style="vertical-align: top;">Write Address<br>
|
|
</td>
|
<tr>
|
<td style="vertical-align: top;">SRAM<br>
|
<td style="vertical-align: top;"><br> </td>
|
</td>
|
<td style="vertical-align: top;">Ram Select<br> </td>
|
<td style="vertical-align: top;">_WADDR <br>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
</td>
|
<td style="vertical-align: top;">_CS<br> </td>
|
</tr>
|
</tr>
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
<tr>
|
<td style="vertical-align: top;">Write Data<br>
|
<td style="vertical-align: top;"><br> </td>
|
</td>
|
<td style="vertical-align: top;">Write Enable<br> </td>
|
<td style="vertical-align: top;">SRAM<br>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
</td>
|
<td style="vertical-align: top;">_WR<br> </td>
|
<td style="vertical-align: top;">_WDATA<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Read Data<br>
|
|
</td>
|
|
<td style="vertical-align: top;">SRAM<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_RDATA<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Ram Select<br>
|
|
</td>
|
|
<td style="vertical-align: top;">SRAM<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_CS<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Write Enable<br>
|
|
</td>
|
|
<td style="vertical-align: top;">SRAM<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_WR<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Read Enable<br>
|
|
</td>
|
|
<td style="vertical-align: top;">SRAM<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_RD<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Bit Write Enable<br>
|
|
</td>
|
|
<td style="vertical-align: top;">SRAM<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_BE<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Clock<br>
|
|
</td>
|
|
<td style="vertical-align: top;">SRAM<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_CLK<br>
|
|
</td>
|
</tr>
|
</tr>
|
|
|
|
|
<tr>
|
|
<td style="vertical-align: top;"><br> </td>
|
|
<td style="vertical-align: top;">Read Enable<br> </td>
|
|
<td style="vertical-align: top;">SRAM<br> </td>
|
|
<td style="vertical-align: top;">_RD<br> </td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td style="vertical-align: top;"><br> </td>
|
|
<td style="vertical-align: top;">Bit Write Enable<br> </td>
|
|
<td style="vertical-align: top;">SRAM<br> </td>
|
|
<td style="vertical-align: top;">_BE<br> </td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td style="vertical-align: top;"><br> </td>
|
|
<td style="vertical-align: top;">Clock<br> </td>
|
|
<td style="vertical-align: top;">SRAM<br> </td>
|
|
<td style="vertical-align: top;">_CLK<br> </td>
|
|
</tr>
|
|
|
|
|
|
|
|
</tbody>
|
</tbody>
|
</table>
|
</table>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
|
<h3 class="western">Wishbone Bus <br>
|
<h3 class="western">Wishbone Bus <br></h3>
|
</h3>
|
<p><br>
|
<p><br>
|
The wishbone bus provides microprocessor interconnection .<br>
|
The wishbone bus provides microprocessor interconnection .<br>
|
</p>
|
</p>
|
<br>
|
<br>
|
<table style="text-align: left; width: 500px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
|
<table style="text-align: left; width: 500px; height: 120px;" border="8"
|
|
cellpadding="4" cellspacing="4">
|
<tbody>
|
<tbody>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;">Interface<br> </td>
|
<td style="vertical-align: top;">Interface<br>
|
<td style="vertical-align: top;">Wishbone<br> </td>
|
</td>
|
<td style="vertical-align: top;">Name<br> </td>
|
<td style="vertical-align: top;">Wishbone<br>
|
<td style="vertical-align: top;">Sub <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">Name<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;">Sub <br>
|
<td style="vertical-align: top;">Address<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
</tr>
|
<td style="vertical-align: top;">_ADR<br> </td>
|
<tr>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;">Address<br>
|
<td style="vertical-align: top;">Write Data<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;">WB<br>
|
<td style="vertical-align: top;"> _WDAT<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">_ADR<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
</tr>
|
<td style="vertical-align: top;">Read Data<br> </td>
|
<tr>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">_RDAT<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">Write Data<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;">WB<br>
|
<td style="vertical-align: top;">Write Enable<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;"> _WDAT<br>
|
<td style="vertical-align: top;">_WE<br> </td>
|
</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;"><br>
|
<td style="vertical-align: top;">Byte Select<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;">Read Data<br>
|
<td style="vertical-align: top;">_SEL<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">WB<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;">_RDAT<br>
|
<td style="vertical-align: top;">Cycle<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
</tr>
|
<td style="vertical-align: top;">_CYC<br> </td>
|
<tr>
|
</tr>
|
<td style="vertical-align: top;"><br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;">Write Enable<br>
|
<td style="vertical-align: top;">Data Strobe<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;">WB<br>
|
<td style="vertical-align: top;">_STB<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">_WE<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
</tr>
|
<td style="vertical-align: top;">Acknowledge<br> </td>
|
<tr>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;"><br>
|
<td style="vertical-align: top;">_ACK<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">Byte Select<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;">WB<br>
|
<td style="vertical-align: top;">CTI<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;">_SEL<br>
|
<td style="vertical-align: top;">_CTI<br> </td>
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Cycle<br>
|
|
</td>
|
|
<td style="vertical-align: top;">WB<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_CYC<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Data Strobe<br>
|
|
</td>
|
|
<td style="vertical-align: top;">WB<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_STB<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Acknowledge<br>
|
|
</td>
|
|
<td style="vertical-align: top;">WB<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_ACK<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">CTI<br>
|
|
</td>
|
|
<td style="vertical-align: top;">WB<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_CTI<br>
|
|
</td>
|
</tr>
|
</tr>
|
</tbody>
|
</tbody>
|
</table>
|
</table>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
<p></p>
|
<p></p>
|
<br>
|
<br>
|
<br>
|
<br>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
