| Line 18... |
Line 18... |
</h2>
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</h2>
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<h2><a name="manifesto"></a>Verification Guidelines</h2>
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<h2><a name="manifesto"></a>Verification Guidelines</h2>
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<p><br>
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<p><br>
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<br>
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<br>
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</p>
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</p>
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<p>Verification is the art of stimulating a component
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<p>Verification is the process of stimulating a component
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module and checking that it produces the correct outputs. Stimulations
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module and checking that it produces the correct outputs. Stimulations
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are designed to
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are designed to
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ensure that all of the components functions are exercised and any
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ensure that all of the components functions are exercised and any
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deviation from the expected behaviour is reported as an error.
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deviation from the expected behaviour is reported as an error.
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Every
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Every
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| Line 164... |
Line 164... |
<li><big>Message
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<li><big>Message
|
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|
|
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|
|
|
|
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</big><br>
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</big><br>
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</li>
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</li>
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</ul>
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</ul>
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<br style="font-family: serif;">
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<br style="font-family: serif;">
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<br style="font-family: serif;">
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<br style="font-family: serif;">
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| Line 182... |
Line 183... |
style="font-family: serif;"><br>
|
style="font-family: serif;"><br>
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<br>
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<br>
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<br>
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<br>
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<span style="font-family: serif;"> </span></code><span
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<span style="font-family: serif;"> </span></code><span
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style="font-family: serif;"><code><span style="font-family: serif;">Do
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style="font-family: serif;"><code><span style="font-family: serif;">Do
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not interweave threads in the test_define blocks. Each block should
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not interweave threads in the test_define blocks. Each fork/join block
|
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should
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only access a single BFM.</span><br style="font-family: serif;">
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only access a single BFM.</span><br style="font-family: serif;">
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<br style="font-family: serif;">
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<br style="font-family: serif;">
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<br style="font-family: serif;">
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<br style="font-family: serif;">
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<span style="font-family: serif;"> Plan on designs where you will
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<span style="font-family: serif;"> Plan on designs where you will
|
need to test multiple instances of a component</span><br
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need to test multiple instances of a component</span><br
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| Line 247... |
Line 249... |
</p>
|
</p>
|
<big><code>
|
<big><code>
|
./sim<br>
|
./sim<br>
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+/bin<br>
|
+/bin<br>
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Makefile<br>
|
Makefile<br>
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+/bench<br>
|
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+verilog<br>
|
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TestBench<br>
|
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+models<br>
|
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model1<br>
|
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model2<br>
|
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.<br>
|
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.<br>
|
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.<br>
|
|
+/lib<br>
|
+/lib<br>
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+lib_part1<br>
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+lib_part1<br>
|
lib_part(s).v<br>
|
lib_part(s).v<br>
|
+lib_part2<br>
|
+lib_part2<br>
|
.<br>
|
.<br>
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.<br>
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.<br>
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.<br>
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.<br>
|
</code><code> +/run</code><br>
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</code><code> +/run</code><br>
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<code> +test_case1<br>
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<code> +/test_case1<br>
|
filelist<br>
|
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dmp_define<br>
|
dmp_define<br>
|
modellist<br>
|
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dut<br>
|
|
test_define<br>
|
test_define<br>
|
liblist<br>
|
+/test_case2<br>
|
TB.defs<br>
|
|
+test_case2<br>
|
|
.<br>
|
|
.<br>
|
.<br>
|
.<br>
|
.<br>
|
+/log<br>
|
+/xml<br>
|
test_case1.log<br>
|
</code><code> test_case1.xml<br>
|
test_case2.log<br>
|
test_case2.xml<br>
|
.<br>
|
|
.<br>
|
|
.<br>
|
|
+/out<br>
|
|
</code><code> test_case1.vcd<br>
|
|
test_case2.vcd<br>
|
|
.<br>
|
.<br>
|
.<br>
|
.<br>
|
.</code><br>
|
.</code><br>
|
</big>
|
</big>
|
<code><ouabache design="" works=""><big><br>
|
<code><ouabache design="" works=""><br>
|
<br>
|
|
<br>
|
|
</big>
|
|
<br>
|
|
</ouabache></code>
|
</ouabache></code>
|
<p>Each component will have a ./sim directory for the test suite.
|
<p>Each component will have a ./sim directory for the test suite.
|
Typing:<br>
|
Typing:<br>
|
</p>
|
</p>
|
<p><big><big><br>
|
<p><big><big><br>
|
| Line 499... |
Line 476... |
`include
|
`include
|
"../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v"<br>
|
"../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v"<br>
|
`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v"<br>
|
`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v"<br>
|
</p>
|
</p>
|
<code style="font-family: monospace;"></code>
|
<code style="font-family: monospace;"></code>
|
<span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
|
<span style="font-family: monospace;">-------------------------------------------------------------------------------------------------------------------------------------</span>
|
<p><br>
|
<p></p>
|
</p>
|
|
<p>The filelist uses `include statements to load all the rtl files into
|
|
the simulation.The paths are relative from the test_case run
|
|
directory. Note that all the verilog files have been post-processed and
|
|
search directories or include directories are not needed.
|
|
</p>
|
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<h2><a name="manifesto"></a>liblist</h2>
|
<h2><a name="manifesto"></a>liblist</h2>
|
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
|
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
|
</p>
|
</p>
|
| Line 1304... |
Line 1275... |
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p></p>
|
<br>
|
<p></p>
|
</p>
|
|
<p><br>
|
|
<br>
|
|
</p>
|
|
<p><br>
|
|
</p>
|
|
<p><br>
|
|
</p>
|
|
<p><br>
|
|
</p>
|
|
<p>This is a test<br>
|
|
</p>
|
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
