| Line 22... |
Line 22... |
</p>
|
</p>
|
<p>Verification is the art of stimulating a component
|
<p>Verification is the art of stimulating a component
|
module and checking that it produces the correct outputs. Stimulations
|
module and checking that it produces the correct outputs. Stimulations
|
are designed to
|
are designed to
|
ensure that all of the components functions are exercised and any
|
ensure that all of the components functions are exercised and any
|
deviation from the expected value is reported as an error. Every
|
deviation from the expected behaviour is reported as an error.
|
|
Every
|
component must have at least one test case but may have as many as
|
component must have at least one test case but may have as many as
|
needed to fully verify the design.<br>
|
needed to fully verify the design. All components will have at least
|
|
one interface and a bus functional model (bfm) must be created for each
|
|
and every interface.<br>
|
</p>
|
</p>
|
<p>A complete test suite is required for every component module.
|
<p>A complete test suite is required for every component module.
|
Each test_case is simulated and the log file will indicate whether the
|
Each test_case is simulated and the log file will indicate whether the
|
test passed or failed. Other output files such as dump files may also
|
test passed or failed. Other output files such as dump files may also
|
be produced duging the simulation.<br>
|
be produced duging the simulation.<br>
|
| Line 83... |
Line 86... |
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p>Every interface on the component is connected to it's own bfm model
|
<p>Every interface on the component is connected to it's own bfm model
|
that contains all the tasks needed to test the interface. The calling
|
that contains all the tasks needed to test the interface. The calling
|
sequences needed to preform a particular test are all loaded from a
|
sequences needed to preform a particular test are all loaded from a
|
sperate file. It is important that each interface has its task calls in
|
sperate test_define file. It is important that each interface has its
|
a seperate code block. The goal is to develope these models and task
|
task calls in
|
|
a seperate code block in the test_define file. The goal is to develop
|
|
these models and task
|
calls on the component simulation and then reuse them as the
|
calls on the component simulation and then reuse them as the
|
component is used in larger designs. Interleaving task calls for
|
component is used in larger designs. Interleaving task calls for
|
different models makes that difficult.<br>
|
different models makes that difficult.<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
|
</p>
|
|
<h2><a name="manifesto"></a>Protocol checkers and monitors<br>
|
|
</h2>
|
|
<br>
|
|
|
|
Protocol checkers and monitors are similar to a bus functional
|
|
models except that they are for obsevation only and cannot
|
|
control any signals. They watch every transaction that occurs on the
|
|
interface and reports a failure when anything violates that interfaces
|
|
defined protocols. <span style="font-family: serif;"> They are created
|
|
in a seperate module and may be instantiated in the testbench and
|
|
connected to an interface.<br>
|
|
<br>
|
|
The same protocol checker can also be included in the rtl code so it
|
|
can monitor an interface that is buried deep inside a chip. Once
|
|
inserted in the rtl source it will watch for and report errors
|
|
that may occur during the regression suite. Since protocol checkers
|
|
are not synthesizable they must be excluded from synthesis with a
|
|
`ifndef SYNTHESYS statement.<br>
|
|
<br>
|
|
Monitors are similar to protocol checkers except that they are designed
|
|
to be implemetent in actual logic. If they ever fire during
|
|
product usage then these events should be latched and saved for later
|
|
debugging.<br>
|
|
<br>
|
|
</span>
|
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<h2><a name="manifesto"></a>guidelines for creating reusable test_cases<br>
|
<h2><a name="manifesto"></a>guidelines for creating reusable test_cases<br>
|
| Line 130... |
Line 162... |
<li><big>Message Type This is either
|
<li><big>Message Type This is either
|
ERROR or WARNING. No type indicates informational message</big></li>
|
ERROR or WARNING. No type indicates informational message</big></li>
|
<li><big>Message
|
<li><big>Message
|
|
|
|
|
|
|
|
|
</big><br>
|
</big><br>
|
</li>
|
</li>
|
</ul>
|
</ul>
|
<br style="font-family: serif;">
|
<br style="font-family: serif;">
|
<br style="font-family: serif;">
|
<br style="font-family: serif;">
|
| Line 168... |
Line 202... |
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
|
<h2><a name="manifesto"></a>Gate and Post Route Simulations<br>
|
|
</h2>
|
|
<br>
|
|
All signals between the DUT and the bfms change only at the
|
|
rising edge of clk. This is fine for RTL sims but will not work for
|
|
real logic with setup and hold time requirements. For these the signals
|
|
driving the dut must be delayed from clk and from each other to provide
|
|
the required setup and hold times. Signals from the DUT will have
|
|
delays and must only be tested during a prescribed time window.<br>
|
|
This is accomplished with a set of modules that mimic the functions of
|
|
a IC tester. These modules provide the interface between the BFM's and
|
|
the DUT.<br>
|
|
<br>
|
|
<br>
|
|
<img style="width: 800px; height: 600px;" alt=""
|
|
src="../png/ver_fig4.png"><br>
|
|
<br style="font-family: serif;">
|
|
<br style="font-family: serif;">
|
|
<span style="font-family: serif;"></span><span
|
|
style="font-family: serif;"><br>
|
|
</span>
|
|
<p></p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
| Line 480... |
Line 536... |
<h2><a name="manifesto"></a>modellist</h2>
|
<h2><a name="manifesto"></a>modellist</h2>
|
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
|
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
|
</p>
|
</p>
|
<code><br>
|
<code><br>
|
`include "../../bench/verilog/models/clock_gen.v"<br>
|
`include "../../bench/verilog/models/clock_gen.v"<br>
|
`include "../../bench/verilog/models/ps2_model.v" <br>
|
`include "../../bench/verilog/models/ps2_model.v"<br>
|
|
</code><code>`include "../../bench/verilog/models/uart_model.v"</code><code>
|
|
<br>
|
`include "../../bench/verilog/models/iobuftri.v" <br>
|
`include "../../bench/verilog/models/iobuftri.v" <br>
|
</code><span style="font-family: monospace;"></span><code><br>
|
</code><span style="font-family: monospace;"></span><code><br>
|
</code>
|
</code>
|
<span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
|
<span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
|
<br>
|
<br>
|
| Line 493... |
Line 551... |
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<h2><a name="manifesto"></a>dut<br>
|
<h2><a name="manifesto"></a>dut<br>
|
</h2>
|
</h2>
|
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span></p>
|
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><code><br>
|
<p><code>reg
|
|
device_write;<br>
|
|
reg [7:0] device_tx_data;<br>
|
|
reg device_parity;<br>
|
|
reg device_ack;<br>
|
|
reg device_stop;<br>
|
|
wire device_rx_read;<br>
|
|
wire [7:0] device_rx_data;<br>
|
|
wire device_rx_parity;<br>
|
|
wire ps2_data_pad_oe;<br>
|
wire ps2_data_pad_oe;<br>
|
wire ps2_data_pad_in;<br>
|
wire ps2_data_pad_in;<br>
|
wire ps2_data;<br>
|
wire ps2_data;<br>
|
wire ps2_clk_pad_oe;<br>
|
wire ps2_clk_pad_oe;<br>
|
wire ps2_clk_pad_in;<br>
|
wire ps2_clk_pad_in;<br>
|
wire ps2_clk;<br>
|
wire ps2_clk;<br>
|
<br>
|
<br>
|
<br>
|
|
<br>
|
|
wire [7:0] portaout;<br>
|
wire [7:0] portaout;<br>
|
wire [7:0] portbout;<br>
|
wire [7:0] portbout;<br>
|
wire [7:0] portcout;<br>
|
wire [7:0] portcout;<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
| Line 531... |
Line 578... |
ms_left; <br>
|
ms_left; <br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
wire
|
wire
|
txd_pad_out;<br>
|
serial_txd;<br>
|
wire
|
wire
|
rxd_pad_in;<br>
|
serial_rxd;<br>
|
wire
|
wire loop;<br>
|
cts_pad_in;<br>
|
<br>
|
wire
|
|
rts_pad_out; <br>
|
|
<br>
|
<br>
|
<br>
|
|
// Instantiate one CPU to be tested.<br>
|
|
soc_mouse<br>
|
soc_mouse<br>
|
#(<br>
|
#(<br>
|
.ROM_WORDS ( `ROM_WORDS ), <br>
|
.ROM_WORDS ( `ROM_WORDS ), <br>
|
.ROM_ADDR ( `ROM_ADDR ), <br>
|
.ROM_ADDR ( `ROM_ADDR ), <br>
|
.ROM_WIDTH ( `ROM_WIDTH ), <br>
|
.ROM_WIDTH ( `ROM_WIDTH ), <br>
|
.ROM_FILE ( `ROM_FILE )<br>
|
.ROM_FILE ( `ROM_FILE )<br>
|
)<br>
|
)<br>
|
dut(<br>
|
dut(<br>
|
.clk (
|
.clk (
|
clk ),<br>
|
clk ),<br>
|
.reset (
|
.reset (
|
reset ),<br>
|
reset ),<br>
|
<br>
|
<br>
|
.ps2_data_pad_in ( ps2_data_pad_in ),<br>
|
.ps2_data_pad_in ( ps2_data_pad_in ),<br>
|
.ps2_clk_pad_in ( ps2_clk_pad_in ),<br>
|
.ps2_clk_pad_in ( ps2_clk_pad_in ),<br>
|
<br>
|
<br>
|
.ps2_data_pad_oe ( ps2_data_pad_oe ),<br>
|
.ps2_data_pad_oe ( ps2_data_pad_oe ),<br>
|
.ps2_clk_pad_oe ( ps2_clk_pad_oe ),<br>
|
.ps2_clk_pad_oe ( ps2_clk_pad_oe ),<br>
|
<br>
|
<br>
|
<br>
|
.portaout (
|
.portaout ( portaout ),<br>
|
portaout ),<br>
|
.portbout ( portbout ),<br>
|
.portbout ( portbout
|
.portcout ( portcout ),<br>
|
),<br>
|
<br>
|
.portcout (
|
<br>
|
portcout ),<br>
|
.y_pos (
|
<br>
|
y_pos ),<br>
|
.y_pos (
|
.x_pos (
|
y_pos ),<br>
|
x_pos ),<br>
|
.x_pos (
|
.new_packet ( new_packet ),<br>
|
x_pos ),<br>
|
.ms_mid (
|
.new_packet ( new_packet
|
ms_mid ), <br>
|
),<br>
|
.ms_right ( ms_right
|
.ms_mid (
|
|
ms_mid ), <br>
|
|
.ms_right (
|
|
ms_right
|
), <br>
|
), <br>
|
.ms_left (
|
.ms_left (
|
ms_left ), <br>
|
ms_left ), <br>
|
<br>
|
|
<br>
|
|
<br>
|
<br>
|
.txd_pad_out ( loop1 ),<br>
|
.txd_pad_out (
|
.rxd_pad_in (
|
serial_txd ),<br>
|
loop1 ),<br>
|
.rxd_pad_in (
|
.cts_pad_in (
|
serial_rxd ),<br>
|
loop2 ),<br>
|
.cts_pad_in (
|
.rts_pad_out ( loop2
|
loop
|
|
),<br>
|
|
.rts_pad_out (
|
|
loop
|
) <br>
|
) <br>
|
<br>
|
<br>
|
);<br>
|
);<br>
|
|
</code></p>
|
|
<p><code>uart_model <br>
|
|
#(.CLKCNT(4'hc))<br>
|
|
uart_model<br>
|
|
(<br>
|
|
|
|
.clk
|
|
(
|
|
clk
|
|
),<br>
|
|
|
|
.reset
|
|
(
|
|
reset
|
|
),
|
<br>
|
<br>
|
|
|
|
.txd_in
|
|
|
|
( serial_txd ),<br>
|
|
|
|
.rxd_out
|
|
|
|
( serial_rxd )<br>
|
<br>
|
<br>
|
|
);</code><br>
|
|
<code></code></p>
|
|
<p><code><br>
|
|
</code></p>
|
|
<p><code><br>
|
iobuftri<br>
|
iobuftri<br>
|
data_tri_buf<br>
|
data_tri_buf<br>
|
(<br>
|
(<br>
|
.i (
|
.i (
|
1'b0 ),<br>
|
1'b0 ),<br>
|
| Line 620... |
Line 695... |
pullup ua1(ps2_data);<br>
|
pullup ua1(ps2_data);<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
ps2_model <br>
|
ps2_model <br>
|
#(.CLKCNT(10'h177))<br>
|
#(.CLKCNT(10'h177))<br>
|
ps2<br>
|
ps2_model<br>
|
(<br>
|
(<br>
|
|
|
.clk
|
.clk
|
(
|
(
|
clk
|
clk
|
| Line 634... |
Line 709... |
(
|
(
|
reset
|
reset
|
),
|
),
|
<br>
|
<br>
|
|
|
.send
|
|
(
|
|
device_write
|
|
),<br>
|
|
|
|
.send_data
|
|
(
|
|
device_tx_data
|
|
),<br>
|
|
|
|
.device_parity (
|
|
device_parity ),<br>
|
|
|
|
.device_ack
|
|
(
|
|
device_ack
|
|
),<br>
|
|
|
|
.device_stop
|
|
(
|
|
device_stop
|
|
),<br>
|
|
|
|
.device_rx_read (
|
|
device_rx_read ),<br>
|
|
|
|
.device_rx_data (
|
|
device_rx_data ),<br>
|
|
.device_rx_parity (
|
|
device_rx_parity ),<br>
|
|
<br>
|
|
|
|
.ps2_clk
|
.ps2_clk
|
(
|
(
|
ps2_clk
|
ps2_clk
|
),<br>
|
),<br>
|
|
|
.ps2_data
|
.ps2_data
|
(
|
(
|
ps2_data
|
ps2_data
|
)<br>
|
)<br>
|
<br>
|
<br>
|
);<br>
|
);</code></p>
|
|
<p><code><br>
|
|
</code></p>
|
|
<p><code><br>
|
</code><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
|
</code><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
|
</p>
|
</p>
|
<p>This file is a verilog code segment that declares all the wires and
|
<p>This file is a verilog code segment that declares all the wires and
|
regs needed in the sim (except for clk and reset). It then
|
regs needed in the sim (except for clk and reset). It then
|
instantiates the component and all needed models for the simulation.<br>
|
instantiates the component and all needed models for the simulation.<br>
|
| Line 696... |
Line 742... |
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span></p>
|
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span></p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p><span style="font-family: monospace;">initial</span><br
|
<p><span style="font-family: monospace;">initial</span><br
|
style="font-family: monospace;">
|
style="font-family: monospace;">
|
<span style="font-family: monospace;">begin</span><br
|
<span style="font-family: monospace;">begin</span><span
|
style="font-family: monospace;">
|
style="font-family: monospace;"></span><br
|
<span style="font-family: monospace;"> `TIMEFORMAT</span><br
|
|
style="font-family: monospace;">
|
style="font-family: monospace;">
|
<span style="font-family: monospace;">$display("
|
<span style="font-family: monospace;">$display("
|
");</span><br style="font-family: monospace;">
|
");</span><br style="font-family: monospace;">
|
<span style="font-family: monospace;">$display("
|
<span style="font-family: monospace;">$display("
|
===================================================");</span><br
|
===================================================");</span><br
|
