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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<title>start</title>
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<title>Reset System Design</title>
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<meta name="GENERATOR" content="OpenOffice.org 3.0 (Linux)">
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<meta name="GENERATOR" content="OpenOffice.org 3.0 (Linux)">
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<meta name="CREATED" content="0;0">
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<meta name="CREATED" content="0;0">
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<meta name="CHANGED" content="20100309;9305300">
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<meta name="CHANGED" content="20100309;9305300">
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<meta name="KEYWORDS" content="start">
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<meta name="Info 3" content="">
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</p>
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</p>
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<br>
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<br>
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<h3 class="western">All components must come out of reset on exactly
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<h3 class="western">All components must come out of reset on exactly
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the same clock<br>
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the same clock<br>
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</h3>
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</h3>
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Thats true, or at least it was back in the 60's. Back then every
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That's true, or at least it was back in the 60's. Back then every
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component would come out of reset and start "componenting". The reset
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component would come out of reset and start "componenting". The reset
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system acted like a conductor so that everybody started on the
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system acted like a conductor so that everybody started on the
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same beat. Those types of systems are rare today. Most major chips have
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same beat. Those types of systems are rare today. Most major chips have
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one or more microprocessors in side so components come out of reset
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one or more microprocessors in side so components come out of reset
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only to sit there waiting for the cpu to configure them and get them
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only to sit there waiting for the cpu to configure them and get them
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<br>
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<br>
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<br>
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<br>
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<h3 class="western">You must design your logic using synchronous design
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<h3 class="western">You must design your logic using synchronous design
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methods<br>
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methods<br>
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</h3>
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</h3>
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Absolutely. Todays chips are huge. The only way that you can close
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Absolutely. Today's chips are huge. The only way that you can close
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timing on a large design is if everyone follows strict synchronous
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timing on a large design is if everyone follows strict synchronous
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design rules. The mistake that many of todays designers make is
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design rules. The mistake that many of todays designers make is
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that they think that because they have to design an asynchronous reset
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that they think that because they have to design an asynchronous reset
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system that they get an exemption from following the rules for
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system that they get an exemption from following the rules for
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synchronous design. Sorry guys, it not one or the other its BOTH.
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synchronous design. Sorry guys, it not one or the other its BOTH.
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That used to be true. The first thing a vendor does when they get a net
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That used to be true. The first thing a vendor does when they get a net
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list is to run a full drc that looks for dft issues. If anybody has any
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list is to run a full drc that looks for dft issues. If anybody has any
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signals crossing between the async reset port on a flipflop and
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signals crossing between the async reset port on a flipflop and
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either a D or a Q port then it flags it as a violation. So you can
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either a D or a Q port then it flags it as a violation. So you can
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either send it back to the customer and wait a week for them to find
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either send it back to the customer and wait a week for them to find
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it, fix it, and resynthesizes or you can eco in a test mux at the flop
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it, fix it, and re-synthesizes or you can eco in a test mux at the flop
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and have it fixed in 5 minutes. Everyone took the easy way out.<br>
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and have it fixed in 5 minutes. Everyone took the easy way out.<br>
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<br>
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<br>
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But then along came Logic equivalence checking (LEC). The final
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But then along came Logic equivalence checking (LEC). The final
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routed net list will be sent back and compared with the customers
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routed net list will be sent back and compared with the customers
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golden net list and all of these ecos will show up in the report.
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golden net list and all of these ecos will show up in the report.
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in a known state but it is lousy when dealing with unknowns. There are
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in a known state but it is lousy when dealing with unknowns. There are
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times like this when it is possible to resolve a X into a known
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times like this when it is possible to resolve a X into a known
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value and it can't. There are also times when it will resolve an
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value and it can't. There are also times when it will resolve an
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X to a known value when it shouldn't. The only way to use verilog is to
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X to a known value when it shouldn't. The only way to use verilog is to
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start with everything in a known state and stop it when anything goes
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start with everything in a known state and stop it when anything goes
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X. That means theres a problem and nothing downstream from that X
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X. That means there's a problem and nothing downstream from that
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X
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can be trusted.<br>
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can be trusted.<br>
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<br>
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<br>
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<br>
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<br>
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You do not prove your reset system design in gates sims. You prove the
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You do not prove your reset system design in gates sims. You prove the
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design in rtl sims and use LEC to prove that gates matches the design
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design in rtl sims and use LEC to prove that gates matches the design
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</ul>
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</ul>
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You are looking at activity that is measured in the milliseconds on a
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You are looking at activity that is measured in the milliseconds on a
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system clock that is measured in the nanoseconds. Performing a reset in
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system clock that is measured in the nanoseconds. Performing a reset in
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one clock cycle requires adding logic to every single flipflop<br>
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one clock cycle requires adding logic to every single flipflop<br>
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for no good reason. A designer should only add reset logic as a last
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for no good reason. A designer should only add reset logic as a last
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resort. The prefered method is to use the existing mission mode logic
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resort. The preferred method is to use the existing mission mode logic
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to perform the reset. If you have a computational block with a fifty
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to perform the reset. If you have a computational block with a fifty
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stage deep pipeline then reset should force it's inputs to 0 and open
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stage deep pipeline then reset should force it's inputs to 0 and open
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all the gates so that every flipflop will be flushed out in 50 clocks.
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all the gates so that every flipflop will be flushed out in 50 clocks.
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Better yet would be to have the block feeding your input force it's
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Better yet would be to have the block feeding your input force it's
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output to all 0's during reset.<br>
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output to all 0's during reset.<br>
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<li>The reset signal has a metastable filter to sync it with
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<li>The reset signal has a metastable filter to sync it with
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the clock.<br>
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the clock.<br>
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</li>
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</li>
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</ul>
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</ul>
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The last is important because some designers will forget that the
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The last is important because some designers will forget that the
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filtered output is actually it's own seperate reset domain<br>
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filtered output is actually it's own separate reset domain<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<h3 class="western">3) Define a known good state<br>
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<h3 class="western">3) Define a known good state<br>
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</ul>
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</ul>
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<ul>
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<ul>
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<li>an active low on the output of the metastable filter</li>
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<li>an active low on the output of the metastable filter</li>
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</ul>
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</ul>
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<br>
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<br>
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The jtag reset is not included because it doesnt reset the timer.
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The jtag reset is not included because it doesn't reset the
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timer.
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Once this step is complete it will provide a map for the reset
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Once this step is complete it will provide a map for the reset
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distribution tree that you will need. The best way to distribute the
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distribution tree that you will need. The best way to distribute the
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reset over a large design is to use what is called a "synchronous reset
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reset over a large design is to use what is called a "synchronous reset
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tree".<br>
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tree".<br>
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<br>
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<br>
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async one will enter reset one cycle before the sync one
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async one will enter reset one cycle before the sync one
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but they will both exit on at the same time. <br>
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but they will both exit on at the same time. <br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<h3 class="western">6) Select reset style for each flip/flop<br>
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</h3>
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We now need to select a reset "Style" for each flip/flop from the four
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possible reset styles.<br>
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<br>
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<br>
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<ul>
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<li>Synchronous</li>
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<li>Synchronous with output override</li>
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<li>Asynchronous</li>
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<li>Both Synchronous and Asynchronous</li>
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</ul>
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<br>
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<br>
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If the reset system is synchronous then you may choose any of the four
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styles. If it is asynchronous then you cannot use the synchronous style.<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<img style="width: 800px; height: 600px;" alt=""
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src="../png/reset_fig1.png"><br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<h3 class="western">7) Apply DFT fixes to all asynchronous ports<br>
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</h3>
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All paths from the Q output of a flip/flop to the asynchronous
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reset/preset port of a flip/flop must be disabled during scan testing.
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The use of a test mux to do this is not recommended because anytime you
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use a test mux you are not testing the circuit as it is used in mission
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mode. There will always be at least one point of failure inside the
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test mux where scan tests will pass but the IC will not function.<br>
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<br>
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The recommended method is to gate off the synchronous path with a atg
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test signal and then recombine it with an asynchronous reset so that
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the async reset it self is still testable. The lib module
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cde_asyncdisable is available for this purpose. DO NOT CREATE YOUR OWN
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TEST LOGIC. Checking the rtl code to ensure that all asynchronous
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resets are testable requires a fairly sophisticated and expensive tool.
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Checking the rtl to ensure that all asynchronous resets are properly
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connected to a cde_asyncdisable module takes a simple perl script.<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<img style="width: 800px; height: 600px;" alt=""
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src="../png/reset_fig2.png"><br>
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<br>
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<br>
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<p><br>
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<p><br>
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<br>
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<br>
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</p>
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</p>
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<p><br>
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<p><br>
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