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https://opencores.org/ocsvn/socgen/socgen/trunk
[/] [socgen/] [trunk/] [tools/] [regtool/] [gen_registers] - Diff between revs 131 and 134
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| Rev 131 |
Rev 134 |
| Line 424... |
Line 424... |
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print OUTFILE " /*********************************************/ \n";
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print OUTFILE " /*********************************************/ \n";
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print OUTFILE "\n\nmodule `${ip_name_base_macro}`";
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print OUTFILE "\n\nmodule `${ip_name_base_macro}`";
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print OUTFILE uc(${memmap_name});
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print OUTFILE uc(${memmap_name});
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print OUTFILE "\n";
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print OUTFILE "\n";
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print OUTFILE "#( parameter UNSELECTED = {${addblk_width}{1'b1}},\n";
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print OUTFILE "#( parameter UNSELECTED = {${byte_size}{1'b1}},\n";
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print OUTFILE " parameter UNMAPPED = {${addblk_width}{1'b0}}";
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print OUTFILE " parameter UNMAPPED = {${byte_size}{1'b0}}";
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| Line 656... |
Line 656... |
}
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}
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}
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}
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# print OUTFILE " input wire [${addblk_numaddbits}-1:${adr_base}] addr";
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#/**********************************************************************/
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#/**********************************************************************/
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#/* */
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#/* */
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#/* write data register creation */
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#/* write data register creation */
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| Line 1886... |
Line 1886... |
my $t_create = $6;
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my $t_create = $6;
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my $t_access = $7;
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my $t_access = $7;
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my $t_has_read = $8;
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my $t_has_read = $8;
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my $t_has_write = $9;
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my $t_has_write = $9;
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my $REG_NAME = uc($t_name);
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my $REG_NAME = uc($t_name);
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print OUTFILE "assign ${t_name}_cs = cs && ( addr >= ${REG_NAME} ) && ( addr < ${REG_NAME}_END );\n";
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print OUTFILE "assign ${t_name}_cs = cs && ( addr[$addblk_numaddbits-1:${adr_base}] >= ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] ) && ( addr[$addblk_numaddbits-1:${adr_base}] < ${REG_NAME}_END[$addblk_numaddbits-1:${adr_base}] );\n";
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}
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}
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}
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}
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print OUTFILE "\n /* verilator lint_on UNSIGNED */ \n";
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print OUTFILE "\n /* verilator lint_on UNSIGNED */ \n";
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