| Line 53... |
Line 53... |
use Cwd;
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use Cwd;
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use XML::LibXML;
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use XML::LibXML;
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use lib './tools';
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use lib './tools';
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use sys::lib;
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use sys::lib;
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use yp::lib;
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use yp::lib;
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use Parallel::ForkManager;
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$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
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$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
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############################################################################
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############################################################################
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| Line 71... |
Line 72... |
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##############################################################################
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##############################################################################
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## Help option
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## Help option
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##############################################################################
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##############################################################################
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if ( $opt_h or $opt_help )
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if ( $opt_h or $opt_help )
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{ print "\n build_master";
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{ print "\n build_elab_master";
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print "\n";
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print "\n";
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exit 1;
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exit 1;
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}
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}
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| Line 91... |
Line 92... |
#/* modules that it uses are saved. */
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#/* modules that it uses are saved. */
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#/* */
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#/* */
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#/* */
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#/* */
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#/**********************************************************************/
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#/**********************************************************************/
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my @elab_cmds = ();
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my @des_cmds = ();
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my @gen_cmds = ();
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my $number_of_cpus = yp::lib::get_number_of_cpus();
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my $home = cwd();
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my $home = cwd();
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my $prefix = yp::lib::get_workspace();
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my $prefix = yp::lib::get_workspace();
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$prefix = "/${prefix}";
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$prefix = "/${prefix}";
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| Line 111... |
Line 118... |
{
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{
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my $library_status = yp::lib::get_library_status($vendor,$library);
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my $library_status = yp::lib::get_library_status($vendor,$library);
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if($library_status eq "active")
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if($library_status eq "active")
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{
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{
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print "$vendor $library \n ";
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# print "$vendor $library \n ";
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run_vendor_library ( $vendor , $library)
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run_vendor_library ( $vendor , $library)
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}
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}
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}
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}
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}
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}
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}
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}
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| Line 137... |
Line 144... |
my $socgen_filename = yp::lib::find_componentConfiguration($vendor,$library,$component);
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my $socgen_filename = yp::lib::find_componentConfiguration($vendor,$library,$component);
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if($socgen_filename)
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if($socgen_filename)
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{
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{
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my $socgen_file = $parser->parse_file($socgen_filename);
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my $socgen_file = $parser->parse_file($socgen_filename);
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#print "ELAB_XXXXX build_master $vendor $library \n";
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#/*********************************************************************************************/
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#/ elaborate each testbench */
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#/ */
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#/*********************************************************************************************/
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foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
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{
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my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;
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my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
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my $testbench_configuration = $j_name ->findnodes('../socgen:configuration/text()')->to_literal ;
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my $testbench_instance = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;
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my $testbench_bus_name = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;
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if(defined $testbench_configuration )
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{
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$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -configuration configuration -env sim -tool testbenches -unit testbench \n";
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}
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else
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{
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$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool testbenches -unit testbench \n";
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}
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push @elab_cmds, $cmd;
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$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n ";
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push @gen_cmds, $cmd;
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$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n ";
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push @des_cmds, $cmd;
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if ($testbench_instance)
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{
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$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name ";
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push @gen_cmds, $cmd;
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}
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}
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#/*********************************************************************************************/
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#/*********************************************************************************************/
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#/ files for simulation */
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#/ elaborate for each test */
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#/ */
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#/ */
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#/*********************************************************************************************/
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#/*********************************************************************************************/
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foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:icarus/socgen:test/socgen:name"))
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foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:icarus/socgen:test/socgen:name"))
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{
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{
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| Line 162... |
Line 215... |
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if($test_variant eq $testbench_variant )
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if($test_variant eq $testbench_variant )
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{
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{
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# print "YYYY $prefix $vendor $library $component $testbench_version $test_name \n ";
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# print "YYYY $prefix $vendor $library $component $testbench_version $test_name \n ";
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$cmd ="./tools/verilog/elab_verilog -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool icarus -unit test -name $test_name \n";
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#print "ELAB_XXXXX test_variant $vendor $library \n";
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print "$cmd";
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if (system($cmd)) {}
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$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool icarus -unit test -name $test_name \n";
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# print "$cmd";
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# if (system($cmd)) {}
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push @elab_cmds, $cmd;
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$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -name $test_name \n";
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# print "$cmd";
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# if (system($cmd)) {}
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push @gen_cmds, $cmd;
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$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -name $test_name \n";
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# print "$cmd";
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# if (system($cmd)) {}
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push @des_cmds, $cmd;
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if ($testbench_instance)
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if ($testbench_instance)
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{
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{
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$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name -test_name $test_name ";
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$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name -test_name $test_name ";
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if (system($cmd)) {}
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push @gen_cmds, $cmd;
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}
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}
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}
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}
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}
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#/*********************************************************************************************/
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#/ elaborate each fpga */
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#/ */
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#/*********************************************************************************************/
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foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:fpgas/socgen:fpga/socgen:variant"))
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{
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my $fpga_variant = $j_name ->findnodes('./text()')->to_literal ;
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my $fpga_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
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my $fpga_configuration = $j_name ->findnodes('../socgen:configuration/text()')->to_literal ;
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if(defined $fpga_configuration )
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{
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$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -configuration $fpga_configuration -env syn -tool fpgas -unit fpga \n";
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}
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}
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else
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{
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$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -env syn -tool fpgas -unit fpga \n";
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}
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}
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# push @elab_cmds, $cmd;
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$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} ";
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# push @gen_cmds, $cmd;
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$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} ";
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# push @des_cmds, $cmd;
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}
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#/*********************************************************************************************/
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#/ elaborate for each chip */
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#/ */
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#/*********************************************************************************************/
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foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:ise/socgen:chip/socgen:name"))
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{
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my $chip_name = $i_name ->findnodes('./text()')->to_literal ;
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my $chip_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
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# print "XXXX $vendor $library $component $chip_variant $chip_name \n ";
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foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:fpgas/socgen:fpga/socgen:variant"))
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{
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my $fpga_variant = $j_name ->findnodes('./text()')->to_literal ;
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my $fpga_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
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if($chip_variant eq $fpga_variant )
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{
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# print "YYYY $prefix $vendor $library $component $fpga_version $chip_name \n ";
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#print "ELAB_XXXXX test_variant $vendor $library \n";
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$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -env syn -tool ise -unit chip -name $chip_name \n";
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# print "$cmd";
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push @elab_cmds, $cmd;
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$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -name $chip_name \n";
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# print "$cmd";
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push @gen_cmds, $cmd;
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$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -name $chip_name \n";
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# print "$cmd";
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push @des_cmds, $cmd;
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}
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}
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}
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}
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}
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}
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}
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@elab_cmds = sys::lib::trim_sort(@elab_cmds);
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@des_cmds = sys::lib::trim_sort(@des_cmds);
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@gen_cmds = sys::lib::trim_sort(@gen_cmds);
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#my $manager = new Parallel::ForkManager( $number_of_cpus );
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foreach $cmd (@elab_cmds)
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{
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# $manager->start and next;
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if (system($cmd)) {}
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# $manager->finish;
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}
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#$manager->wait_all_children;
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foreach $cmd (@des_cmds)
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{
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if (system($cmd)) {}
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}
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foreach $cmd (@gen_cmds)
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{
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# $manager->start and next;
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if (system($cmd)) {}
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# $manager->finish;
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}
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}
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#$manager->wait_all_children;
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return(0);
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return(0);
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}
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}
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