OpenCores
URL https://opencores.org/ocsvn/sockit_owm/sockit_owm/trunk

Subversion Repositories sockit_owm

[/] [sockit_owm/] [trunk/] [hdl/] [sockit_owm.v] - Diff between revs 3 and 5

Show entire file | Details | Blame | View Log

Rev 3 Rev 5
Line 377... Line 377...
  else if (pls & (cnt == t_zero))  owr_cyc <= 1'b0;
  else if (pls & (cnt == t_zero))  owr_cyc <= 1'b0;
end
end
 
 
// state counter (initial value depends whether the cycle is reset or data)
// state counter (initial value depends whether the cycle is reset or data)
always @ (posedge clk, posedge rst)
always @ (posedge clk, posedge rst)
if (rst)                 cnt <= 0;
if (rst)                 cnt <= 'd0;
else begin
else begin
  if (bus_wen_ctl_sts)   cnt <= (&bus_wdt[1:0] ? t_idl : bus_wdt[1] ? t_rst : t_bit) - 'd1;
  if (bus_wen_ctl_sts)   cnt <= (&bus_wdt[1:0] ? t_idl : bus_wdt[1] ? t_rst : t_bit) - 'd1;
  else if (pls)          cnt <= cnt - 'd1;
  else if (pls)          cnt <= cnt - 'd1;
end
end
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.