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https://opencores.org/ocsvn/sockit_owm/sockit_owm/trunk
[/] [sockit_owm/] [trunk/] [hdl/] [sockit_owm.v] - Diff between revs 3 and 5
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Rev 5 |
Line 377... |
Line 377... |
else if (pls & (cnt == t_zero)) owr_cyc <= 1'b0;
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else if (pls & (cnt == t_zero)) owr_cyc <= 1'b0;
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end
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end
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// state counter (initial value depends whether the cycle is reset or data)
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// state counter (initial value depends whether the cycle is reset or data)
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always @ (posedge clk, posedge rst)
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always @ (posedge clk, posedge rst)
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if (rst) cnt <= 0;
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if (rst) cnt <= 'd0;
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else begin
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else begin
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if (bus_wen_ctl_sts) cnt <= (&bus_wdt[1:0] ? t_idl : bus_wdt[1] ? t_rst : t_bit) - 'd1;
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if (bus_wen_ctl_sts) cnt <= (&bus_wdt[1:0] ? t_idl : bus_wdt[1] ? t_rst : t_bit) - 'd1;
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else if (pls) cnt <= cnt - 'd1;
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else if (pls) cnt <= cnt - 'd1;
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end
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end
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