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//////////////////////////////////////////////////////////////////////////////
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// //
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// Minimalistic 1-wire (onewire) master with Avalon MM bus interface //
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// //
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// Copyright (C) 2010 Iztok Jeras //
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// //
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//////////////////////////////////////////////////////////////////////////////
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// //
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// This RTL is free hardware: you can redistribute it and/or modify //
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// it under the terms of the GNU Lesser General Public License //
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// as published by the Free Software Foundation, either //
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// version 3 of the License, or (at your option) any later version. //
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// //
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// This RTL is distributed in the hope that it will be useful, //
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// but WITHOUT ANY WARRANTY; without even the implied warranty of //
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
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// GNU General Public License for more details. //
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// //
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// You should have received a copy of the GNU General Public License //
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// along with this program. If not, see <http://www.gnu.org/licenses/>. //
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// //
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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// //
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// The clock divider parameter is computed with the next formula: //
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// //
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// CDR_N = f_CLK * BTP_N - 1 (example: CDR_N = 1MHz * 5.0us - 1 = 5-1) //
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// CDR_O = f_CLK * BTP_O - 1 (example: CDR_O = 1MHz * 1.0us - 1 = 1-1) //
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// //
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// If the dividing factor is not a round integer, than the timing of the //
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// controller will be slightly off, and would support only a subset of //
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// 1-wire devices with timing closer to the typical 30us slot. //
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// //
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// Base time periods BTP_N = "5.0" and BTP_O = "1.0" are optimized for //
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// onewire timing. The default timing restricts the range of available //
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// frequences to multiples of 1MHz. //
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// //
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// If even this restrictions are too strict use timing BTP_N = "6.0" and //
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// BTP_O = "0.5", where the actual periods can be in the range: //
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// 6.0us <= BTP_N <= 7.5us //
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// 0.5us <= BTP_O <= 0.66us //
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// //
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// A third timing option is available for normal mode BTP_N = "7.5", this //
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// option is optimized for logic size. //
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// //
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//////////////////////////////////////////////////////////////////////////////
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module sockit_owm #(
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// enable implementation of optional functionality
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parameter OVD_E = 1, // overdrive functionality is implemented by default
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parameter CDR_E = 1, // clock divider register is implemented by default
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// interface parameters
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parameter BDW = 32, // bus data width
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parameter OWN = 1, // number of 1-wire ports
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// computed bus address port width
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`ifdef __ICARUS__
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parameter BAW = (BDW==32) ? 1 : 2,
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`else
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parameter BAW = 1, // TODO, the above is correct, but does not work well with Altera SOPC Builder
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`endif
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// base time period
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parameter BTP_N = "5.0", // normal mode (5.0us, options are "7.5", "5.0" and "6.0")
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parameter BTP_O = "1.0", // overdrive mode (1.0us, options are "1.0", and "0.5")
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// normal mode timing
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parameter T_RSTH_N = (BTP_N == "7.5") ? 64 : (BTP_N == "5.0") ? 96 : 80, // reset high
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parameter T_RSTL_N = (BTP_N == "7.5") ? 64 : (BTP_N == "5.0") ? 96 : 80, // reset low
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parameter T_RSTP_N = (BTP_N == "7.5") ? 10 : (BTP_N == "5.0") ? 15 : 10, // reset presence pulse
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parameter T_DAT0_N = (BTP_N == "7.5") ? 8 : (BTP_N == "5.0") ? 12 : 10, // bit 0 low
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parameter T_DAT1_N = (BTP_N == "7.5") ? 1 : (BTP_N == "5.0") ? 1 : 1, // bit 1 low
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parameter T_BITS_N = (BTP_N == "7.5") ? 2 : (BTP_N == "5.0") ? 3 : 2, // bit sample
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parameter T_RCVR_N = (BTP_N == "7.5") ? 1 : (BTP_N == "5.0") ? 1 : 1, // recovery
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parameter T_IDLE_N = (BTP_N == "7.5") ? 128 : (BTP_N == "5.0") ? 200 : 160, // idle timer
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// overdrive mode timing
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parameter T_RSTH_O = (BTP_O == "1.0") ? 48 : 96, // reset high
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parameter T_RSTL_O = (BTP_O == "1.0") ? 48 : 96, // reset low
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parameter T_RSTP_O = (BTP_O == "1.0") ? 10 : 15, // reset presence pulse
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parameter T_DAT0_O = (BTP_O == "1.0") ? 6 : 12, // bit 0 low
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parameter T_DAT1_O = (BTP_O == "1.0") ? 1 : 2, // bit 1 low
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parameter T_BITS_O = (BTP_O == "1.0") ? 2 : 3, // bit sample
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parameter T_RCVR_O = (BTP_O == "1.0") ? 2 : 4, // recovery
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parameter T_IDLE_O = (BTP_O == "1.0") ? 96 : 192, // idle timer
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// clock divider ratios (defaults are for a 2MHz clock)
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parameter CDR_N = 5-1, // normal mode
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parameter CDR_O = 1-1 // overdrive mode
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)(
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// system signals
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input clk,
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input rst,
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// CPU bus interface
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input bus_ren, // read enable
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input bus_wen, // write enable
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input [BAW-1:0] bus_adr, // address
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input [BDW-1:0] bus_wdt, // write data
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output [BDW-1:0] bus_rdt, // read data
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output bus_irq, // interrupt request
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// 1-wire interface
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output [OWN-1:0] owr_p, // output power enable
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output [OWN-1:0] owr_e, // output pull down enable
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input [OWN-1:0] owr_i // input from bidirectional wire
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);
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//////////////////////////////////////////////////////////////////////////////
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// local parameters
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//////////////////////////////////////////////////////////////////////////////
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// size of combined power and select registers
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localparam PDW = (BDW==32) ? 24 : 8;
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// size of boudrate generator counter (divider for normal mode is largest)
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localparam CDW = CDR_E ? ((BDW==32) ? 16 : 8) : $clog2(CDR_N);
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// size of port select signal
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localparam SDW = $clog2(OWN);
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// size of cycle timing counter
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localparam TDW = (T_RSTH_O+T_RSTL_O) > (T_RSTH_N+T_RSTL_N)
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? $clog2(T_RSTH_O+T_RSTL_O) : $clog2(T_RSTH_N+T_RSTL_N);
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//////////////////////////////////////////////////////////////////////////////
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// local signals
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//////////////////////////////////////////////////////////////////////////////
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// address dependent write enable
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wire bus_ren_ctl_sts;
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wire bus_wen_ctl_sts;
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wire bus_wen_pwr_sel;
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wire bus_wen_cdr_n;
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wire bus_wen_cdr_o;
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// read data bus segments
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wire [7:0] bus_rdt_ctl_sts;
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wire [PDW-1:0] bus_rdt_pwr_sel;
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// clock divider
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reg [CDW-1:0] div;
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reg [CDW-1:0] cdr_n;
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reg [CDW-1:0] cdr_o;
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wire pls;
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// cycle control and status
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reg owr_cyc; // cycle status
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reg [TDW-1:0] cnt; // cycle counter
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// port select
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//generate if (OWN>1) begin : sel_declaration
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reg [SDW-1:0] owr_sel;
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//end endgenerate
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// modified input data for overdrive
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wire req_ovd;
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// onewire signals
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reg [OWN-1:0] owr_pwr; // power
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reg owr_ovd; // overdrive
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reg owr_rst; // reset
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reg owr_dat; // data bit
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reg owr_smp; // sample bit
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reg owr_oen; // output enable
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wire owr_iln; // input line
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// interrupt signals
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reg irq_ena; // interrupt enable
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reg irq_sts; // interrupt status
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// timing signals
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wire [TDW-1:0] t_idl ; // idle cycle time
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wire [TDW-1:0] t_rst ; // reset cycle time
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wire [TDW-1:0] t_bit ; // data bit cycle time
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wire [TDW-1:0] t_rstp; // reset presence pulse sampling time
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wire [TDW-1:0] t_rsth; // reset release time
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wire [TDW-1:0] t_dat0; // data bit 0 release time
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wire [TDW-1:0] t_dat1; // data bit 1 release time
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wire [TDW-1:0] t_bits; // data bit sampling time
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wire [TDW-1:0] t_zero; // end of cycle time
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//////////////////////////////////////////////////////////////////////////////
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// cycle timing
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//////////////////////////////////////////////////////////////////////////////
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// idle time
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assign t_idl = req_ovd ? T_IDLE_O : T_IDLE_N ;
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// reset cycle time (reset low + reset hight)
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assign t_rst = req_ovd ? T_RSTL_O + T_RSTH_O : T_RSTL_N + T_RSTH_N ;
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// data bit cycle time (write 0 + recovery)
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assign t_bit = req_ovd ? T_DAT0_O + + T_RCVR_O : T_DAT0_N + T_RCVR_N;
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// reset presence pulse sampling time (reset high - reset presence)
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assign t_rstp = owr_ovd ? T_RSTH_O - T_RSTP_O : T_RSTH_N - T_RSTP_N ;
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// reset release time (reset high)
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assign t_rsth = owr_ovd ? T_RSTH_O : T_RSTH_N ;
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// data bit 0 release time (write bit 0 - write bit 0 + recovery)
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assign t_dat0 = owr_ovd ? T_DAT0_O - T_DAT0_O + T_RCVR_O : T_DAT0_N - T_DAT0_N + T_RCVR_N;
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// data bit 1 release time (write bit 0 - write bit 1 + recovery)
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assign t_dat1 = owr_ovd ? T_DAT0_O - T_DAT1_O + T_RCVR_O : T_DAT0_N - T_DAT1_N + T_RCVR_N;
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// data bit sampling time (write bit 0 - write bit 1 + recovery)
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assign t_bits = owr_ovd ? T_DAT0_O - T_BITS_O + T_RCVR_O : T_DAT0_N - T_BITS_N + T_RCVR_N;
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// end of cycle time
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assign t_zero = 'd0;
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//////////////////////////////////////////////////////////////////////////////
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// bus read
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//////////////////////////////////////////////////////////////////////////////
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// bus segnemt - controll/status register
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assign bus_rdt_ctl_sts = {irq_ena, irq_sts, 1'b0, owr_pwr[0], owr_cyc, owr_ovd, owr_rst, owr_dat};
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// bus segnemt - power and select register
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generate
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if (BDW==32) begin
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if (OWN>1) begin
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assign bus_rdt_pwr_sel = {{16-OWN{1'b0}}, owr_pwr, 4'h0, {4-SDW{1'b0}}, owr_sel};
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end else begin
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assign bus_rdt_pwr_sel = 24'h0000_00;
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end
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end else if (BDW==8) begin
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if (OWN>1) begin
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assign bus_rdt_pwr_sel = {{ 4-OWN{1'b0}}, owr_pwr, {4-SDW{1'b0}}, owr_sel};
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end else begin
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assign bus_rdt_pwr_sel = 8'hxx;
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end
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end
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endgenerate
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// bus read data
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generate if (BDW==32) begin
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assign bus_rdt = (bus_adr[0]==1'b0) ? {bus_rdt_pwr_sel, bus_rdt_ctl_sts} : (cdr_o << 16 | cdr_n);
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end else if (BDW==8) begin
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assign bus_rdt = (bus_adr[1]==1'b0) ? ((bus_adr[0]==1'b0) ? bus_rdt_ctl_sts
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: bus_rdt_pwr_sel)
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: ((bus_adr[0]==1'b0) ? cdr_n
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: cdr_o );
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end endgenerate
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//////////////////////////////////////////////////////////////////////////////
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// bus write
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//////////////////////////////////////////////////////////////////////////////
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// combined write/read enable and address decoder
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generate if (BDW==32) begin
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assign bus_ren_ctl_sts = bus_ren & bus_adr[0] == 1'b0;
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assign bus_wen_ctl_sts = bus_wen & bus_adr[0] == 1'b0;
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assign bus_wen_pwr_sel = bus_wen & bus_adr[0] == 1'b0;
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assign bus_wen_cdr_n = bus_wen & bus_adr[0] == 1'b1;
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assign bus_wen_cdr_o = bus_wen & bus_adr[0] == 1'b1;
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end else if (BDW==8) begin
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assign bus_ren_ctl_sts = bus_ren & bus_adr[1:0] == 2'b00;
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assign bus_wen_ctl_sts = bus_wen & bus_adr[1:0] == 2'b00;
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assign bus_wen_pwr_sel = bus_wen & bus_adr[1:0] == 2'b01;
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assign bus_wen_cdr_n = bus_wen & bus_adr[1:0] == 2'b10;
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assign bus_wen_cdr_o = bus_wen & bus_adr[1:0] == 2'b11;
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end endgenerate
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//////////////////////////////////////////////////////////////////////////////
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// clock divider
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//////////////////////////////////////////////////////////////////////////////
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// clock divider ratio registers
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generate
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if (CDR_E) begin
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if (BDW==32) begin
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always @ (posedge clk, posedge rst)
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if (rst) begin
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cdr_n <= CDR_N;
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cdr_o <= CDR_O;
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end else begin
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if (bus_wen_cdr_n) cdr_n <= bus_wdt[15: 0];
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if (bus_wen_cdr_o) cdr_o <= bus_wdt[31:16];
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end
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end else if (BDW==8) begin
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always @ (posedge clk, posedge rst)
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if (rst) begin
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cdr_n <= CDR_N;
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cdr_o <= CDR_O;
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end else begin
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if (bus_wen_cdr_n) cdr_n <= bus_wdt;
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if (bus_wen_cdr_o) cdr_o <= bus_wdt;
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end
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end
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end else begin
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initial begin
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cdr_n = CDR_N;
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cdr_o = CDR_O;
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end
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end
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endgenerate
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// clock divider
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always @ (posedge clk, posedge rst)
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if (rst) div <= 'd0;
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else begin
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if (bus_wen) div <= 'd0;
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else div <= pls ? 'd0 : div + owr_cyc;
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end
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// divided clock pulse
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assign pls = (div == (owr_ovd ? cdr_o : cdr_n));
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//////////////////////////////////////////////////////////////////////////////
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// power and select register
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//////////////////////////////////////////////////////////////////////////////
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// select and power register implementation
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generate if (OWN>1) begin : sel_implementation
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// port select
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always @ (posedge clk, posedge rst)
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if (rst) owr_sel <= {SDW{1'b0}};
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else if (bus_wen_pwr_sel) owr_sel <= bus_wdt[(BDW==32 ? 8 : 0)+:SDW];
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// power delivery
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always @ (posedge clk, posedge rst)
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if (rst) owr_pwr <= {OWN{1'b0}};
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else if (bus_wen_pwr_sel) owr_pwr <= bus_wdt[(BDW==32 ? 16 : 4)+:OWN];
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end else begin
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// port select
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initial owr_sel <= 'd0;
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// power delivery
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always @ (posedge clk, posedge rst)
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if (rst) owr_pwr <= 1'b0;
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else if (bus_wen_ctl_sts) owr_pwr <= bus_wdt[4];
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end endgenerate
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//////////////////////////////////////////////////////////////////////////////
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// interrupt logic
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//////////////////////////////////////////////////////////////////////////////
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// bus interrupt
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assign bus_irq = irq_ena & irq_sts;
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// interrupt enable
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always @ (posedge clk, posedge rst)
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if (rst) irq_ena <= 1'b0;
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else if (bus_wen_ctl_sts) irq_ena <= bus_wdt[7];
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// transmit status (active after onewire cycle ends)
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always @ (posedge clk, posedge rst)
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if (rst) irq_sts <= 1'b0;
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else begin
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if (bus_wen_ctl_sts) irq_sts <= 1'b0;
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else if (pls & (cnt == t_zero)) irq_sts <= 1'b1;
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else if (bus_ren_ctl_sts) irq_sts <= 1'b0;
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end
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//////////////////////////////////////////////////////////////////////////////
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// onewire state machine
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//////////////////////////////////////////////////////////////////////////////
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assign req_ovd = OVD_E ? bus_wen_ctl_sts & bus_wdt[2] : 1'b0;
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// overdrive
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always @ (posedge clk, posedge rst)
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if (rst) owr_ovd <= 1'b0;
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else if (bus_wen_ctl_sts) owr_ovd <= req_ovd;
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// reset
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always @ (posedge clk, posedge rst)
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if (rst) owr_rst <= 1'b0;
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else if (bus_wen_ctl_sts) owr_rst <= bus_wdt[1];
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// transmit data, reset, overdrive
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always @ (posedge clk, posedge rst)
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if (rst) owr_dat <= 1'b0;
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else begin
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if (bus_wen_ctl_sts) owr_dat <= bus_wdt[0];
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else if (pls & (cnt == t_zero)) owr_dat <= owr_smp;
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end
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// onewire cycle status
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always @ (posedge clk, posedge rst)
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if (rst) owr_cyc <= 1'b0;
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else begin
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if (bus_wen_ctl_sts) owr_cyc <= bus_wdt[3] & ~&bus_wdt[2:0];
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else if (pls & (cnt == t_zero)) owr_cyc <= 1'b0;
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end
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// state counter (initial value depends whether the cycle is reset or data)
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always @ (posedge clk, posedge rst)
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if (rst) cnt <= 0;
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else begin
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if (bus_wen_ctl_sts) cnt <= (&bus_wdt[1:0] ? t_idl : bus_wdt[1] ? t_rst : t_bit) - 'd1;
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else if (pls) cnt <= cnt - 'd1;
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end
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// receive data (sampling point depends whether the cycle is reset or data)
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always @ (posedge clk)
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if (pls) begin
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if ( owr_rst & (cnt == t_rstp)) owr_smp <= owr_iln; // presence detect
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else if (~owr_rst & (cnt == t_bits)) owr_smp <= owr_iln; // read data bit
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end
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// output register (switch point depends whether the cycle is reset or data)
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always @ (posedge clk, posedge rst)
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if (rst) owr_oen <= 1'b0;
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else begin
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if (bus_wen_ctl_sts) owr_oen <= ~&bus_wdt[1:0];
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else if (pls) begin
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if (owr_rst & (cnt == t_rsth)) owr_oen <= 1'b0; // reset
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else if (owr_dat & (cnt == t_dat1)) owr_oen <= 1'b0; // write 1, read
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else if ( (cnt == t_dat0)) owr_oen <= 1'b0; // write 0
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end
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end
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//////////////////////////////////////////////////////////////////////////////
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// IO
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//////////////////////////////////////////////////////////////////////////////
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// only one 1-wire line cn be accessed at the same time
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assign owr_e = owr_oen << owr_sel;
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// all 1-wire lines can be powered independently
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assign owr_p = owr_pwr;
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// 1-wire line status read multiplexer
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assign owr_iln = owr_i [owr_sel];
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endmodule
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