URL
https://opencores.org/ocsvn/sockit_owm/sockit_owm/trunk
[/] [sockit_owm/] [trunk/] [sim/] [iverilog_gtkwave.scr] - Diff between revs 2 and 3
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#!/bin/bash
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# cleanup first
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rm onewire.out
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rm onewire.vcd
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# list of source files
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sources="../hdl/onewire_tb.v ../hdl/onewire_slave_model.v ../hdl/sockit_owm.v"
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# compile verilog sources (testbench and RTL) and run simulation
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# data bus widths
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for buswdth in "BDW_32" "BDW_8"
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do
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# clock divider implementation
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for divider in "CDR_NONE" "CDR_E"
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do
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# timing options
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for preset in "PRESET_50_10" "PRESET_60_05" "PRESET_75"
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do
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iverilog -o onewire.out $sources -D$preset -D$divider -D$buswdth
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vvp onewire.out -none
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done
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done
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done
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# test a single 1-wire line configuration (waveform generation is enabled)
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iverilog -o onewire.out $sources -DPRESET_50_10 -DCDR_NONE -DBDW_32 -DOWN=1
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vvp onewire.out
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# open the waveform and detach it
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gtkwave onewire.vcd gtkwave.sav &
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