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---====================== Start Software License ========================---
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--== ==--
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--== This license governs the use of this software, and your use of ==--
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--== this software constitutes acceptance of this license. Agreement ==--
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--== with all points is required to use this software. ==--
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--== ==--
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--== 1. This source file may be used and distributed without ==--
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--== restriction provided that this software license statement is not ==--
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--== removed from the file and that any derivative work contains the ==--
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--== original software license notice and the associated disclaimer. ==--
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--== ==--
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--== 2. This source file is free software; you can redistribute it ==--
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--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==--
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--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==--
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--== This implies modification and/or derivative work of this Software. ==--
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--== ==--
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--== 3. This source is distributed in the hope that it will be useful, ==--
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--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==--
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--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==--
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--== ==--
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--== Your rights under this license are terminated immediately if you ==--
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--== breach it in any way. ==--
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--== ==--
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---======================= End Software License =========================---
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---====================== Start Copyright Notice ========================---
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--== ==--
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--== Filename ..... receive_fifo.vhd ==--
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--== Download ..... http://www.ida.ing.tu-bs.de ==--
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--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
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--== Authors ...... Björn Osterloh, Karel Kotarowski ==--
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--== Contact ...... Björn Osterloh (b.osterloh@tu-bs.de) ==--
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--== Copyright .... Copyright (c) 2008 IDA ==--
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--== Project ...... SoCWire CODEC ==--
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--== Version ...... 1.00 ==--
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--== Conception ... 11 November 2008 ==--
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--== Modified ..... N/A ==--
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--== ==--
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---======================= End Copyright Notice =========================---
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE WORK.ALL;
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ENTITY receive_fifo IS
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GENERIC(
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datawidth : NATURAL RANGE 8 TO 8192
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);
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PORT(
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--== General Interface (Sync Rst, 50MHz Clock) ==--
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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--== SoCWire Interface ==--
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state : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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--== Data Input Interface ==--
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dat_full : OUT STD_LOGIC;
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dat_nwrite : IN STD_LOGIC;
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dat_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
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--== Data Output Interface ==--
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dat_nread : IN STD_LOGIC;
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dat_empty : OUT STD_LOGIC;
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dat_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
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--== FCT Output Interface ==--
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fct_nread : IN STD_LOGIC;
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fct_empty : OUT STD_LOGIC
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);
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END receive_fifo;
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ARCHITECTURE rtl OF receive_fifo IS
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---==========================---
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--== Constants Declarations ==--
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---==========================---
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CONSTANT st_error_reset : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
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CONSTANT st_error_wait : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
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CONSTANT st_ready : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
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CONSTANT st_started : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
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CONSTANT st_connecting : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
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CONSTANT st_run : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101";
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CONSTANT st_unknown_1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "110";
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CONSTANT st_unknown_2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
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CONSTANT zeros : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 1) := (OTHERS => '0');
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---=======================---
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--== Signal Declarations ==--
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---=======================---
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SIGNAL rd_en : STD_LOGIC;
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SIGNAL rd_addr : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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SIGNAL rd_empty_d : STD_LOGIC;
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SIGNAL rd_empty : STD_LOGIC;
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SIGNAL rd_addr_d : STD_LOGIC_VECTOR(9 DOWNTO 0);
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SIGNAL wr_en : STD_LOGIC;
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SIGNAL wr_addr : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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SIGNAL wr_full_d : STD_LOGIC;
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SIGNAL wr_full : STD_LOGIC;
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SIGNAL wr_din : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
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SIGNAL wr_addr_d : STD_LOGIC_VECTOR(9 DOWNTO 0);
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SIGNAL empty_i : STD_LOGIC;
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SIGNAL fct_empty_i_d : STD_LOGIC;
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SIGNAL fct_empty_i : STD_LOGIC;
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SIGNAL fct_en : STD_LOGIC;
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SIGNAL credit : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
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SIGNAL credit_d : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
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SIGNAL credit_e : STD_LOGIC;
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SIGNAL vfullness : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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SIGNAL vfullness_d : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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SIGNAL vfullness_e : STD_LOGIC;
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SIGNAL fullness : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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SIGNAL fullness_d : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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SIGNAL fullness_e : STD_LOGIC;
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SIGNAL got_eop : STD_LOGIC;
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SIGNAL empty_i_d : STD_LOGIC;
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SIGNAL rst_fct : STD_LOGIC;
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SIGNAL wr_en_ext : STD_LOGIC;
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---=============================================---
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--== Component Instantiations for leaf modules ==--
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---=============================================---
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COMPONENT dp_ram
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GENERIC(
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datawidth : NATURAL RANGE 8 TO 8192
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);
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PORT(
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--== General Interface ==--
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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--== Write Interface ==--
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wr_en : IN STD_LOGIC;
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wr_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
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wr_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
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--== Read Interface ==--
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rd_en : IN STD_LOGIC;
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rd_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
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rd_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0)
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);
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END COMPONENT dp_ram;
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BEGIN
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---============================================---
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--== Reset for non-Connecting & non-Run logic ==--
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---============================================---
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rst_fct <= '1' WHEN (rst = '1') OR NOT((state = st_connecting) OR (state = st_run)) ELSE '0';
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---=====================---
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--== Synchronous Logic ==--
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---=====================---
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PROCESS (clk)
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF rst_fct = '0' THEN
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fct_empty_i <= fct_empty_i_d;
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IF credit_e = '1' THEN
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credit <= credit_d;
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END IF;
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ELSE
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credit <= (others => '0');
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fct_empty_i <= '1';
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END IF;
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IF rst = '0' THEN
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wr_full <= wr_full_d;
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rd_empty <= rd_empty_d;
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empty_i <= empty_i_d;
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IF wr_en = '1' THEN
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got_eop <= wr_din(datawidth);
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wr_addr <= wr_addr_d;
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END IF;
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IF rd_en = '1' THEN
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rd_addr <= rd_addr_d;
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END IF;
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IF fullness_e = '1' THEN
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fullness <= fullness_d;
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END IF;
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IF vfullness_e = '1' THEN
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vfullness <= vfullness_d;
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END IF;
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ELSE
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got_eop <= '1';
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wr_addr <= (others => '0');
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rd_addr <= (others => '0');
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wr_full <= '1';
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rd_empty <= '1';
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fullness <= (others => '0');
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empty_i <= '1';
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vfullness <= (others => '0');
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END IF;
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END IF;
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END PROCESS;
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---=================---
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--== EEP Generator ==--
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---=================---
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wr_din <= dat_din WHEN (dat_nwrite = '0') AND (wr_full = '0') ELSE '1' & zeros & '1';
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---===========================================---
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--== FIFO Write Enable & EEP Insertion Logic ==--
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---===========================================---
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wr_en <= '1' WHEN ((dat_nwrite = '0') AND (wr_full = '0')) OR ((got_eop = '0') AND (state /= st_connecting) AND (state /= st_run)) ELSE '0';
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---======================---
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--== FIFO Write Address ==--
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---======================---
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wr_addr_d <= wr_addr + 1;
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---==================---
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--== FIFO Full Flag ==--
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---==================---
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wr_full_d <= '1' WHEN ((credit(5 DOWNTO 1) = 0) AND ((credit(0) = '0') OR (wr_en_ext = '1')) AND
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(fct_en = '0')) OR (state /= st_run) ELSE '0';
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---===========================---
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--== FIFO (Auto) Read Enable ==--
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---===========================---
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rd_en <= NOT(rd_empty) AND (empty_i OR NOT(dat_nread));
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---=====================---
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--== FIFO Read Address ==--
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---=====================---
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rd_addr_d <= rd_addr + 1;
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---===================---
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--== FIFO Empty Flag ==--
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---===================---
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rd_empty_d <= '1' WHEN (fullness(9 DOWNTO 1) = 0) AND (wr_en = '0') AND
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((fullness(0) = '0') OR (rd_en = '1')) ELSE '0';
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---==================================---
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--== FIFO (Actual) Fullness Counter ==--
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---==================================---
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PROCESS(wr_en, rd_en, fullness)
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BEGIN
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IF (wr_en = '1') THEN
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fullness_d <= fullness + 1;
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ELSIF (rd_en = '1') THEN
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fullness_d <= fullness - 1;
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ELSE
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fullness_d <= fullness;
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END IF;
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END PROCESS;
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fullness_e <= rd_en XOR wr_en;
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---===============================---
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--== Data Output Handshake Logic ==--
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---===============================---
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empty_i_d <= rd_empty AND (empty_i OR NOT(dat_nread));
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---===================================---
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--== FIFO (Virtual) Fullness Counter ==--
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---===================================---
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PROCESS(vfullness, fct_en, rd_en, fullness_d)
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VARIABLE tmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
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BEGIN
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tmp := fct_en & rd_en;
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CASE tmp IS
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WHEN "00" => vfullness_d <= fullness_d;
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WHEN "01" => vfullness_d <= vfullness - 1;
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WHEN "10" => vfullness_d <= vfullness + 8;
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WHEN "11" => vfullness_d <= vfullness + 7;
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WHEN OTHERS => NULL;
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END CASE;
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END PROCESS;
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vfullness_e <= (fct_en OR rd_en) WHEN (state = st_connecting) OR (state = st_run) ELSE '1';
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---===================---
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--== FCT Read Enable ==--
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---===================---
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fct_en <= NOT(fct_nread) AND NOT(fct_empty_i);
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---==========================---
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--== Receive Credit Counter ==--
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---==========================---
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wr_en_ext <= '1' WHEN ((dat_nwrite = '0') AND (wr_full = '0')) ELSE '0';
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PROCESS(credit, fct_en, wr_en_ext)
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VARIABLE tmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
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BEGIN
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tmp := fct_en & wr_en_ext;
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CASE tmp IS
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WHEN "11" => credit_d <= credit + 7;
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WHEN "10" => credit_d <= credit + 8;
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WHEN OTHERS => credit_d <= credit - 1;
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END CASE;
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END PROCESS;
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credit_e <= fct_en OR wr_en_ext;
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---=======================---
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--== FCT Handshake Logic ==--
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---=======================---
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PROCESS(fct_empty_i, fct_nread, credit, vfullness)
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BEGIN
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CASE fct_empty_i IS
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WHEN '0' => IF (fct_nread = '0') THEN
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fct_empty_i_d <= '1';
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ELSE
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fct_empty_i_d <= '0';
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END IF;
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WHEN '1' => IF (credit <= 48) AND (vfullness <= 1014) THEN
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fct_empty_i_d <= '0';
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ELSE
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fct_empty_i_d <= '1';
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END IF;
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WHEN OTHERS => NULL;
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END CASE;
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END PROCESS;
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---=================---
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--== Dual Port RAM ==--
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---=================---
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dp_ram0 : dp_ram
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GENERIC MAP
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( datawidth => datawidth )
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PORT MAP
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(--== General Interface ==--
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rst => rst,
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clk => clk,
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--== Write Interface ==--
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wr_en => wr_en,
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wr_addr => wr_addr,
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wr_din => wr_din,
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--== Read Interface ==--
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rd_en => rd_en,
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rd_addr => rd_addr,
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rd_dout => dat_dout
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);
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---======================================---
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--== Shared Internal & External Signals ==--
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---======================================---
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fct_empty <= fct_empty_i;
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dat_empty <= empty_i;
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dat_full <= wr_full;
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END rtl;
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