OpenCores
URL https://opencores.org/ocsvn/socwire/socwire/trunk

Subversion Repositories socwire

[/] [socwire/] [trunk/] [CODEC/] [socwire_codec.vhd] - Diff between revs 22 and 23

Show entire file | Details | Blame | View Log

Rev 22 Rev 23
Line 46... Line 46... 
USE WORK.ALL;
 
USE WORK.ALL;
 
 
 
 
 
 
 
 
 
ENTITY socwire_codec IS
 
ENTITY socwire_codec IS
 
  GENERIC(
 
  GENERIC(
 
          --== Set Codec Speed to system clock in nanoseconds! ==--
 
 
 
          --== USE GEREIC MAPPING FROM TOPLEVEL!!!             ==--
 
          --== USE GEREIC MAPPING FROM TOPLEVEL!!!             ==--
 
               bitwidth : NATURAL RANGE 8 TO 8192;
 
              datawidth            : NATURAL RANGE 8 TO 8192:=8;
 
               speed    : NATURAL RANGE 1 TO 100
 
         speed                      : NATURAL RANGE 1 TO 100:=10;               -- Set CODEC speed to system clock in nanoseconds !
 
 
 
         after64              : NATURAL RANGE 1 TO 6400:=64;   -- Spacewire Standard 6400 = 6.4 us
 
 
 
         after128             : NATURAL RANGE 1 TO 12800:=128; -- Spacewire Standard 12800 = 12.8 us                              
 
 
              disconnect_detection : NATURAL RANGE 1 TO 850:=85     -- Spacewire Standard 850 = 850 ns
 
         );
 
         );
 
  PORT(
 
  PORT(
 
       --==  General Interface (Sync Rst, 50MHz Clock) ==--
 
       --==  General Interface (Sync Rst, 50MHz Clock) ==--
 
 
 
 
 
       rst        : IN  STD_LOGIC;
 
       rst        : IN  STD_LOGIC;
 
       clk        : IN  STD_LOGIC;
 
       clk        : IN  STD_LOGIC;
 
 
 
 
 
       --== Link Enable Interface ==--
 
       --== Link Enable Interface ==--
 
 
 
 
 
       enable     : IN  STD_LOGIC;
 
       socw_en    : IN  STD_LOGIC;
 
       disable    : IN  STD_LOGIC;
 
       socw_dis   : IN  STD_LOGIC;
 
 
 
 
 
       --== Serial Receive Interface ==--
 
       --== Serial Receive Interface ==--
 
 
 
 
 
       rx         : IN  STD_LOGIC_VECTOR(bitwidth+1 DOWNTO 0);
 
       rx         : IN  STD_LOGIC_VECTOR(datawidth+1 DOWNTO 0);
 
       rx_valid   : IN  STD_LOGIC;
 
       rx_valid   : IN  STD_LOGIC;
 
 
 
 
 
       --== Serial Transmit Interface ==--
 
       --== Serial Transmit Interface ==--
 
 
 
 
 
       tx         : OUT STD_LOGIC_VECTOR(bitwidth+1 DOWNTO 0);
 
       tx         : OUT STD_LOGIC_VECTOR(datawidth+1 DOWNTO 0);
 
       tx_valid   : OUT STD_LOGIC;
 
       tx_valid   : OUT STD_LOGIC;
 
 
 
 
 
       --== Data Input Interface ==--
 
       --== Data Input Interface ==--
 
 
 
 
 
       dat_full   : OUT STD_LOGIC;
 
       dat_full   : OUT STD_LOGIC;
 
       dat_nwrite : IN  STD_LOGIC;
 
       dat_nwrite : IN  STD_LOGIC;
 
       dat_din    : IN  STD_LOGIC_VECTOR(bitwidth DOWNTO 0);
 
       dat_din    : IN  STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
 
 
 
 
       --== Data Output Interface ==--
 
       --== Data Output Interface ==--
 
 
 
 
 
       dat_nread  : IN  STD_LOGIC;
 
       dat_nread  : IN  STD_LOGIC;
 
       dat_empty  : OUT STD_LOGIC;
 
       dat_empty  : OUT STD_LOGIC;
 
       dat_dout   : OUT STD_LOGIC_VECTOR(bitwidth DOWNTO 0);
 
       dat_dout   : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
 
 
 
 
       --== Active Interface ==--
 
       --== Active Interface ==--
 
 
 
 
 
       active     : OUT STD_LOGIC
 
       active     : OUT STD_LOGIC
 
      );
 
      );
Line 131... Line 133... 
--== Signal Declarations (Rx to Rx FIFO) ==--
 
--== Signal Declarations (Rx to Rx FIFO) ==--
 
---=======================================---
 
---=======================================---
 
 
 
 
 
SIGNAL dat_full_i   : STD_LOGIC;
 
SIGNAL dat_full_i   : STD_LOGIC;
 
SIGNAL dat_nwrite_i : STD_LOGIC;
 
SIGNAL dat_nwrite_i : STD_LOGIC;
 
SIGNAL dat_din_i    : STD_LOGIC_VECTOR(bitwidth DOWNTO 0);
 
SIGNAL dat_din_i    : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
 
 
 
 
---=======================================---
 
---=======================================---
 
--== Signal Declarations (Rx FIFO to Tx) ==--
 
--== Signal Declarations (Rx FIFO to Tx) ==--
 
---=======================================---
 
---=======================================---
 
 
 
 
Line 153... Line 155... 
--== Signal Declarations (Tx FIFO to Tx) ==--
 
--== Signal Declarations (Tx FIFO to Tx) ==--
 
---=======================================---
 
---=======================================---
 
 
 
 
 
SIGNAL dat_nread_i : STD_LOGIC;
 
SIGNAL dat_nread_i : STD_LOGIC;
 
SIGNAL dat_empty_i : STD_LOGIC;
 
SIGNAL dat_empty_i : STD_LOGIC;
 
SIGNAL dat_dout_i  : STD_LOGIC_VECTOR(bitwidth DOWNTO 0);
 
SIGNAL dat_dout_i  : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
 
 
 
 
---=============================================---
 
---=============================================---
 
--== TESTBENCH : Type Declarations : TESTBENCH ==--
 
--== TESTBENCH : Type Declarations : TESTBENCH ==--
 
---=============================================---
 
---=============================================---
 
 
 
 
Line 185... Line 187... 
--== Component Instantiations for leaf modules ==--
 
--== Component Instantiations for leaf modules ==--
 
---=============================================---
 
---=============================================---
 
 
 
 
 
COMPONENT receiver
 
COMPONENT receiver
 
  GENERIC(
 
  GENERIC(
 
            bitwidth : NATURAL RANGE 8 TO 8192;
 
            datawidth : NATURAL RANGE 8 TO 8192;
 
            speed        : NATURAL RANGE 1 TO 100
 
            speed        : NATURAL RANGE 1 TO 100;
 
 
 
                        disconnect_detection : NATURAL RANGE 1 TO 850
 
         );
 
         );
 
        PORT(
 
        PORT(
 
       --== General Interface (Sync Rst, 50MHz Clock) ==--
 
       --== General Interface (Sync Rst, 50MHz Clock) ==--
 
 
 
 
 
       rst       : IN  STD_LOGIC;
 
       rst       : IN  STD_LOGIC;
Line 200... Line 203... 
 
 
 
 
       state     : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
 
       state     : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
 
 
 
 
 
       --== External Receive Interface ==--
 
       --== External Receive Interface ==--
 
 
 
 
 
       rx                : IN  STD_LOGIC_VECTOR(bitwidth+1 DOWNTO 0);
 
       rx                : IN  STD_LOGIC_VECTOR(datawidth+1 DOWNTO 0);
 
       rx_valid  : IN  STD_LOGIC;
 
       rx_valid  : IN  STD_LOGIC;
 
 
 
 
 
       --== Character Interface ==--
 
       --== Character Interface ==--
 
 
 
 
 
       got_null  : OUT STD_LOGIC;
 
       got_null  : OUT STD_LOGIC;
Line 221... Line 224... 
 
 
 
 
       --== Data Output Interface ==--
 
       --== Data Output Interface ==--
 
 
 
 
 
       dat_nread : IN  STD_LOGIC;
 
       dat_nread : IN  STD_LOGIC;
 
       dat_empty : OUT STD_LOGIC;
 
       dat_empty : OUT STD_LOGIC;
 
       dat_dout  : OUT STD_LOGIC_VECTOR(bitwidth DOWNTO 0);
 
       dat_dout  : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
 
 
 
 
       --== FCT Output Interface ==--
 
       --== FCT Output Interface ==--
 
 
 
 
 
       fct_nread : IN  STD_LOGIC;
 
       fct_nread : IN  STD_LOGIC;
 
       fct_empty : OUT STD_LOGIC
 
       fct_empty : OUT STD_LOGIC
Line 233... Line 236... 
END COMPONENT;
 
END COMPONENT;
 
 
 
 
 
COMPONENT receive_fifo
 
COMPONENT receive_fifo
 
 
 
 
 
  GENERIC(
 
  GENERIC(
 
          bitwidth : NATURAL RANGE 8 TO 8192
 
          datawidth : NATURAL RANGE 8 TO 8192
 
         );
 
         );
 
 
 
 
 
        PORT(
 
        PORT(
 
       --== General Interface (Sync Rst, 50MHz Clock) ==--
 
       --== General Interface (Sync Rst, 50MHz Clock) ==--
 
 
 
 
Line 250... Line 253... 
 
 
 
 
       --== Data Input Interface ==--
 
       --== Data Input Interface ==--
 
 
 
 
 
       dat_full   : OUT STD_LOGIC;
 
       dat_full   : OUT STD_LOGIC;
 
       dat_nwrite : IN  STD_LOGIC;
 
       dat_nwrite : IN  STD_LOGIC;
 
       dat_din    : IN  STD_LOGIC_VECTOR(bitwidth DOWNTO 0);
 
       dat_din    : IN  STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
 
 
 
 
       --== Data Output Interface ==--
 
       --== Data Output Interface ==--
 
 
 
 
 
       dat_nread  : IN  STD_LOGIC;
 
       dat_nread  : IN  STD_LOGIC;
 
       dat_empty  : OUT STD_LOGIC;
 
       dat_empty  : OUT STD_LOGIC;
 
       dat_dout   : OUT STD_LOGIC_VECTOR(bitwidth DOWNTO 0);
 
       dat_dout   : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
 
 
 
 
       --== FCT Output Interface ==--
 
       --== FCT Output Interface ==--
 
 
 
 
 
       fct_nread  : IN  STD_LOGIC;
 
       fct_nread  : IN  STD_LOGIC;
 
       fct_empty  : OUT STD_LOGIC
 
       fct_empty  : OUT STD_LOGIC
 
      );
 
      );
 
END COMPONENT receive_fifo;
 
END COMPONENT receive_fifo;
 
 
 
 
 
COMPONENT state_machine
 
COMPONENT state_machine
 
    GENERIC(
 
    GENERIC(
 
            speed        : NATURAL RANGE 1 TO 100
 
             speed       : NATURAL RANGE 1 TO 100;
 
 
 
                         after64   : NATURAL RANGE 1 TO 6400;
 
 
 
                         after128  : NATURAL RANGE 1 TO 12800
 
           );
 
           );
 
        PORT(
 
        PORT(
 
       --==  General Interface (Sync Rst, 50MHz Clock) ==--
 
       --==  General Interface (Sync Rst, 50MHz Clock) ==--
 
 
 
 
 
       rst       : IN  STD_LOGIC;
 
       rst       : IN  STD_LOGIC;
 
       clk       : IN  STD_LOGIC;
 
       clk       : IN  STD_LOGIC;
 
 
 
 
 
       --== Link Enable Interface ==--
 
       --== Link Enable Interface ==--
 
 
 
 
 
       enable    : IN  STD_LOGIC;
 
       socw_en    : IN  STD_LOGIC;
 
       disable   : IN  STD_LOGIC;
 
       socw_dis   : IN  STD_LOGIC;
 
 
 
 
 
       --== SoCWire Interface ==--
 
       --== SoCWire Interface ==--
 
 
 
 
 
       state     : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
 
       state     : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
 
 
 
 
Line 306... Line 311... 
      );
 
      );
 
END COMPONENT state_machine;
 
END COMPONENT state_machine;
 
 
 
 
 
COMPONENT transmitter
 
COMPONENT transmitter
 
  GENERIC(
 
  GENERIC(
 
          bitwidth : NATURAL RANGE 8 TO 8192
 
          datawidth : NATURAL RANGE 8 TO 8192
 
         );
 
         );
 
        PORT(
 
        PORT(
 
 
 
 
 
       --== General Interface (Sync Rst, 50MHz Clock) ==--
 
       --== General Interface (Sync Rst, 50MHz Clock) ==--
 
 
 
 
Line 321... Line 326... 
 
 
 
 
       state      : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
 
       state      : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
 
 
 
 
 
       --== External Transmit Interface ==--
 
       --== External Transmit Interface ==--
 
 
 
 
 
       tx                 : OUT STD_LOGIC_VECTOR(bitwidth+1 DOWNTO 0);
 
       tx                 : OUT STD_LOGIC_VECTOR(datawidth+1 DOWNTO 0);
 
       tx_valid   : OUT STD_LOGIC;
 
       tx_valid   : OUT STD_LOGIC;
 
 
 
 
 
       --== Data Input Interface ==--
 
       --== Data Input Interface ==--
 
 
 
 
 
       dat_full   : OUT STD_LOGIC;
 
       dat_full   : OUT STD_LOGIC;
 
       dat_nwrite : IN  STD_LOGIC;
 
       dat_nwrite : IN  STD_LOGIC;
 
       dat_din    : IN  STD_LOGIC_VECTOR(bitwidth DOWNTO 0);
 
       dat_din    : IN  STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
 
 
 
 
       --== FCT Input Interface ==--
 
       --== FCT Input Interface ==--
 
 
 
 
 
       fct_full   : OUT STD_LOGIC;
 
       fct_full   : OUT STD_LOGIC;
 
       fct_nwrite : IN  STD_LOGIC
 
       fct_nwrite : IN  STD_LOGIC
 
      );
 
      );
 
END COMPONENT transmitter;
 
END COMPONENT transmitter;
 
 
 
 
 
COMPONENT transmit_fifo
 
COMPONENT transmit_fifo
 
  GENERIC(
 
  GENERIC(
 
          bitwidth : NATURAL RANGE 8 TO 8192
 
          datawidth : NATURAL RANGE 8 TO 8192
 
         );
 
         );
 
        PORT(
 
        PORT(
 
       --== General Interface (Sync Rst, 50MHz Clock) ==--
 
       --== General Interface (Sync Rst, 50MHz Clock) ==--
 
 
 
 
 
       rst        : IN  STD_LOGIC;
 
       rst        : IN  STD_LOGIC;
Line 355... Line 360... 
 
 
 
 
       --== Data Input Interface ==--
 
       --== Data Input Interface ==--
 
 
 
 
 
       dat_full   : OUT STD_LOGIC;
 
       dat_full   : OUT STD_LOGIC;
 
       dat_nwrite : IN  STD_LOGIC;
 
       dat_nwrite : IN  STD_LOGIC;
 
       dat_din    : IN  STD_LOGIC_VECTOR(bitwidth DOWNTO 0);
 
       dat_din    : IN  STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
 
 
 
 
       --== Data Output Interface ==--
 
       --== Data Output Interface ==--
 
 
 
 
 
       dat_nread  : IN  STD_LOGIC;
 
       dat_nread  : IN  STD_LOGIC;
 
       dat_empty  : OUT STD_LOGIC;
 
       dat_empty  : OUT STD_LOGIC;
 
       dat_dout   : OUT STD_LOGIC_VECTOR(bitwidth DOWNTO 0);
 
       dat_dout   : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
 
 
 
 
       --== FCT Input Interface ==--
 
       --== FCT Input Interface ==--
 
 
 
 
 
       fct_full   : OUT STD_LOGIC;
 
       fct_full   : OUT STD_LOGIC;
 
       fct_nwrite : IN  STD_LOGIC
 
       fct_nwrite : IN  STD_LOGIC
Line 391... Line 396... 
 
 
 
 
  ---======================---
 
  ---======================---
 
  --== SoCWire Receiver ==--
 
  --== SoCWire Receiver ==--
 
  ---======================---
 
  ---======================---
 
 
 
 
 
  U0 : receiver
 
  rx0 : receiver
 
    GENERIC MAP
 
    GENERIC MAP
 
          ( speed => speed,
 
          ( speed => speed,
 
            bitwidth => bitwidth )
 
            datawidth => datawidth,
 
 
 
                disconnect_detection=>disconnect_detection)
 
    PORT MAP
 
    PORT MAP
 
      (--==  General Interface (Sync Rst) ==--
 
      (--==  General Interface (Sync Rst) ==--
 
       rst       => rst,
 
       rst       => rst,
 
       clk       => clk,
 
       clk       => clk,
 
       --== SoCWire Interface ==--
 
       --== SoCWire Interface ==--
Line 428... Line 434... 
 
 
 
 
  ---================---
 
  ---================---
 
  --== Receive FIFO ==--
 
  --== Receive FIFO ==--
 
  ---================---
 
  ---================---
 
 
 
 
 
  U1 : receive_fifo
 
  rx_fifo : receive_fifo
 
      GENERIC MAP
 
      GENERIC MAP
 
          ( bitwidth => bitwidth )
 
          ( datawidth => datawidth )
 
    PORT MAP
 
    PORT MAP
 
      (--==  General Interface (Sync Rst) ==--
 
      (--==  General Interface (Sync Rst) ==--
 
       rst        => rst,
 
       rst        => rst,
 
       clk        => clk,
 
       clk        => clk,
 
       --== SoCWire Interface ==--
 
       --== SoCWire Interface ==--
Line 455... Line 461... 
 
 
 
 
  ---===========================---
 
  ---===========================---
 
  --== SoCWire State Machine ==--
 
  --== SoCWire State Machine ==--
 
  ---===========================---
 
  ---===========================---
 
 
 
 
 
  U2 : state_machine
 
  statem : state_machine
 
    GENERIC MAP
 
    GENERIC MAP
 
          ( speed =>  speed )
 
          (  speed =>  speed,
 
 
 
                 after64 =>after64,
 
 
 
                 after128=>after128)
 
    PORT MAP
 
    PORT MAP
 
      (--==  General Interface (Sync Rst, 50MHz Clock) ==--
 
      (--==  General Interface (Sync Rst, 50MHz Clock) ==--
 
       rst       => rst,
 
       rst       => rst,
 
       clk       => clk,
 
       clk       => clk,
 
       --== Link Enable Interface ==--
 
       --== Link Enable Interface ==--
 
       enable    => enable,
 
       socw_en    => socw_en,
 
       disable   => disable,
 
       socw_dis   => socw_dis,
 
       --== SoCWire Interface ==--
 
       --== SoCWire Interface ==--
 
       state     => state,
 
       state     => state,
 
       --== Character Interface ==--
 
       --== Character Interface ==--
 
       got_null  => got_null,
 
       got_null  => got_null,
 
       got_fct   => got_fct,
 
       got_fct   => got_fct,
Line 486... Line 494... 
 
 
 
 
  ---=========================---
 
  ---=========================---
 
  --== SoCWire Transmitter ==--
 
  --== SoCWire Transmitter ==--
 
  ---=========================---
 
  ---=========================---
 
 
 
 
 
  U3 : transmitter
 
  tx0 : transmitter
 
    GENERIC MAP
 
    GENERIC MAP
 
          ( bitwidth =>  bitwidth )
 
          ( datawidth =>  datawidth )
 
    PORT MAP
 
    PORT MAP
 
      (--== General Interface (Sync Rst, 50MHz Clock) ==--
 
      (--== General Interface (Sync Rst, 50MHz Clock) ==--
 
       rst        => rst,
 
       rst        => rst,
 
       clk        => clk,
 
       clk        => clk,
 
       --== SoCWire Interface ==--
 
       --== SoCWire Interface ==--
Line 512... Line 520... 
 
 
 
 
  ---====================---
 
  ---====================---
 
  --== Transmitter FIFO ==--
 
  --== Transmitter FIFO ==--
 
  ---====================---
 
  ---====================---
 
 
 
 
 
  U4 : transmit_fifo
 
  tx_fifo : transmit_fifo
 
    GENERIC MAP
 
    GENERIC MAP
 
          ( bitwidth =>  bitwidth )
 
          ( datawidth =>  datawidth )
 
    PORT MAP
 
    PORT MAP
 
      (--== General Interface (Sync Rst, 50MHz Clock) ==--
 
      (--== General Interface (Sync Rst, 50MHz Clock) ==--
 
       rst        => rst,
 
       rst        => rst,
 
       clk        => clk,
 
       clk        => clk,
 
       --== SoCWire Interface ==--
 
       --== SoCWire Interface ==--

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.