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---====================== Start Software License ========================---
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--== ==--
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--== This license governs the use of this software, and your use of ==--
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--== this software constitutes acceptance of this license. Agreement ==--
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--== with all points is required to use this software. ==--
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--== ==--
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--== 1. This source file may be used and distributed without ==--
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--== restriction provided that this software license statement is not ==--
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--== removed from the file and that any derivative work contains the ==--
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--== original software license notice and the associated disclaimer. ==--
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--== ==--
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--== 2. This source file is free software; you can redistribute it ==--
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--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==--
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--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==--
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--== This implies modification and/or derivative work of this Software. ==--
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--== ==--
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--== 3. This source is distributed in the hope that it will be useful, ==--
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--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==--
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--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==--
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--== ==--
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--== Your rights under this license are terminated immediately if you ==--
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--== breach it in any way. ==--
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--== ==--
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---======================= End Software License =========================---
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---====================== Start Copyright Notice ========================---
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--== ==--
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--== Filename ..... state_machine.vhd ==--
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--== Download ..... http://www.ida.ing.tu-bs.de ==--
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--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
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--== Authors ...... Björn Osterloh, Karel Kotarowski ==--
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--== Contact ...... Björn Osterloh (b.osterloh@tu-bs.de) ==--
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--== Copyright .... Copyright (c) 2008 IDA ==--
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--== Project ...... SoCWire CODEC ==--
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--== Version ...... 1.00 ==--
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--== Conception ... 11 November 2008 ==--
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--== Modified ..... N/A ==--
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--== ==--
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---======================= End Copyright Notice =========================---
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE WORK.ALL;
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ENTITY state_machine IS
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GENERIC(
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speed : NATURAL RANGE 1 TO 100;
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after64 : NATURAL RANGE 1 TO 6400;
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after128 : NATURAL RANGE 1 TO 12800
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);
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PORT(
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--== General Interface (Sync Rst, 50MHz Clock) ==--
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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--== Link Enable Interface ==--
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socw_en : IN STD_LOGIC;
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socw_dis : IN STD_LOGIC;
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--== SoCWire Interface ==--
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state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
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--== Character Interface ==--
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got_null : IN STD_LOGIC;
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got_fct : IN STD_LOGIC;
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got_nchar : IN STD_LOGIC;
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--== Error Interface ==--
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err_par : IN STD_LOGIC;
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err_esc : IN STD_LOGIC;
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err_dsc : IN STD_LOGIC;
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err_fct : IN STD_LOGIC;
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err_nchar : IN STD_LOGIC;
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--== Active Interface ==--
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active : OUT STD_LOGIC
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);
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END state_machine;
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ARCHITECTURE rtl OF state_machine IS
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---==========================---
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--== Constants Declarations ==--
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---==========================---
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CONSTANT st_error_reset : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
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CONSTANT st_error_wait : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
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CONSTANT st_ready : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
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CONSTANT st_started : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
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CONSTANT st_connecting : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
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CONSTANT st_run : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101";
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CONSTANT st_unknown_1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "110";
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CONSTANT st_unknown_2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
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---=======================---
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--== Signal Declarations ==--
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---=======================---
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SIGNAL state_i : STD_LOGIC_VECTOR(2 DOWNTO 0);
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SIGNAL state_d : STD_LOGIC_VECTOR(2 DOWNTO 0);
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SIGNAL watchdog_r : STD_LOGIC;
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SIGNAL watchdog_d : STD_LOGIC_VECTOR(13 DOWNTO 0);
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SIGNAL watchdog : STD_LOGIC_VECTOR(13 DOWNTO 0);
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BEGIN
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---=====================---
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--== Synchronous Logic ==--
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---=====================---
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PROCESS (clk)
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF rst = '0' THEN
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state_i <= state_d;
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watchdog <= watchdog_d;
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ELSE
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state_i <= (others => '0');
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watchdog <= (others => '0');
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END IF;
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END IF;
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END PROCESS;
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---===========================---
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--== SoCWire State Machine ==--
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---===========================---
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PROCESS(state_i, watchdog, got_fct, got_nchar, err_par, err_esc, err_dsc, err_fct, err_nchar, socw_en, got_null, socw_dis)
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BEGIN
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CASE state_i IS
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WHEN st_error_reset =>
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IF (watchdog = after64 / speed - 1) THEN -- 6.4us Passed
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state_d <= st_error_wait;
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watchdog_r <= '1';
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ELSE
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state_d <= st_error_reset;
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watchdog_r <= '0';
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END IF;
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WHEN st_error_wait =>
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IF (got_fct = '1') OR (got_nchar = '1') OR
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(err_par = '1') OR (err_esc = '1') OR (err_dsc = '1') THEN
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state_d <= st_error_reset;
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watchdog_r <= '1';
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ELSIF (watchdog = after128 / speed - 1) THEN -- 12.8us Passed
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state_d <= st_ready;
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watchdog_r <= '0';
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ELSE
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state_d <= st_error_wait;
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watchdog_r <= '0';
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END IF;
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WHEN st_ready =>
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IF (got_fct = '1') OR (got_nchar = '1') OR
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(err_par = '1') OR (err_esc = '1') OR (err_dsc = '1') THEN
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state_d <= st_error_reset;
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watchdog_r <= '1';
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ELSIF (socw_en = '1') THEN
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state_d <= st_started;
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watchdog_r <= '1';
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ELSE
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state_d <= st_ready;
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watchdog_r <= '0';
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END IF;
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WHEN st_started =>
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IF (got_nchar = '1') OR
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(err_par = '1') OR (err_esc = '1') OR (err_dsc = '1') THEN
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state_d <= st_error_reset;
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watchdog_r <= '1';
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ELSIF (watchdog = after128 / speed - 1) THEN -- 12.8us Passed
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state_d <= st_error_reset;
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watchdog_r <= '1';
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ELSIF (got_null = '1') THEN
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state_d <= st_connecting;
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watchdog_r <= '1';
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ELSE
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state_d <= st_started;
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watchdog_r <= '0';
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END IF;
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WHEN st_connecting =>
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IF (got_nchar = '1') OR
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(err_par = '1') OR (err_esc = '1') OR (err_dsc = '1') THEN
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state_d <= st_error_reset;
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watchdog_r <= '1';
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ELSIF (watchdog = after128 / speed - 1) THEN -- 12.8us Passed
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state_d <= st_error_reset;
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watchdog_r <= '1';
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ELSIF (got_fct = '1') THEN
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state_d <= st_run;
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watchdog_r <= '1';
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ELSE
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state_d <= st_connecting;
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watchdog_r <= '0';
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END IF;
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WHEN st_run =>
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IF (err_fct = '1') OR (err_nchar = '1') OR
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(err_par = '1') OR (err_esc = '1') OR
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(err_dsc = '1') OR (socw_dis = '1') THEN
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state_d <= st_error_reset;
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watchdog_r <= '1';
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ELSE
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state_d <= st_run;
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watchdog_r <= '0';
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END IF;
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WHEN OTHERS =>
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state_d <= st_error_reset;
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watchdog_r <= '1';
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END CASE;
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END PROCESS;
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---====================---
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--== Watchdog Counter ==--
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---====================---
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PROCESS(watchdog_r, watchdog, state_i)
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BEGIN
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IF (watchdog_r = '1') OR (state_i = st_run) OR (state_i = st_ready) THEN
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watchdog_d <= (others => '0');
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ELSE
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watchdog_d <= watchdog + 1;
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END IF;
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END PROCESS;
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---======================================---
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--== Shared Internal & External Signals ==--
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---======================================---
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state <= state_i;
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active <= '1' WHEN (state_i = st_Run) ELSE '0';
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END rtl;
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