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---====================== Start Software License ========================---
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--== ==--
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--== This license governs the use of this software, and your use of ==--
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--== this software constitutes acceptance of this license. Agreement ==--
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--== with all points is required to use this software. ==--
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--== ==--
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--== 1. This source file may be used and distributed without ==--
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--== restriction provided that this software license statement is not ==--
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--== removed from the file and that any derivative work contains the ==--
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--== original software license notice and the associated disclaimer. ==--
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--== ==--
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--== 2. This source file is free software; you can redistribute it ==--
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--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==--
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--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==--
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--== This implies modification and/or derivative work of this Software. ==--
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--== ==--
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--== 3. This source is distributed in the hope that it will be useful, ==--
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--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==--
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--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==--
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--== ==--
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--== Your rights under this license are terminated immediately if you ==--
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--== breach it in any way. ==--
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--== ==--
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---======================= End Software License =========================---
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---====================== Start Copyright Notice ========================---
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--== ==--
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--== Filename ..... transmit_fifo.vhd ==--
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--== Download ..... http://www.ida.ing.tu-bs.de ==--
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--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
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--== Authors ...... Björn Osterloh, Karel Kotarowski ==--
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--== Contact ...... Björn Osterloh (b.osterloh@tu-bs.de) ==--
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--== Copyright .... Copyright (c) 2008 IDA ==--
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--== Project ...... SoCWire CODEC ==--
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--== Version ...... 1.00 ==--
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--== Conception ... 11 November 2008 ==--
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--== Modified ..... N/A ==--
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--== ==--
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---======================= End Copyright Notice =========================---
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE WORK.ALL;
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ENTITY transmit_fifo IS
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GENERIC(
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datawidth : NATURAL RANGE 8 TO 8192
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);
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PORT(
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--== General Interface (Sync Rst, 50MHz Clock) ==--
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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--== SoCWire Interface ==--
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state : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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--== Data Input Interface ==--
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dat_full : OUT STD_LOGIC;
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dat_nwrite : IN STD_LOGIC;
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dat_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
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--== Data Output Interface ==--
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dat_nread : IN STD_LOGIC;
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dat_empty : OUT STD_LOGIC;
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dat_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
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--== FCT Input Interface ==--
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fct_full : OUT STD_LOGIC;
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fct_nwrite : IN STD_LOGIC
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);
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END transmit_fifo;
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ARCHITECTURE rtl OF transmit_fifo IS
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---==========================---
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--== Constants Declarations ==--
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---==========================---
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CONSTANT st_error_reset : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
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CONSTANT st_error_wait : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
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CONSTANT st_ready : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
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CONSTANT st_started : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
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CONSTANT st_connecting : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
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CONSTANT st_run : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101";
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CONSTANT st_unknown_1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "110";
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CONSTANT st_unknown_2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
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---=======================---
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--== Signal Declarations ==--
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---=======================---
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SIGNAL rst_fct : STD_LOGIC;
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SIGNAL fct_full_d : STD_LOGIC;
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SIGNAL fct_full_i : STD_LOGIC;
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SIGNAL fct_en : STD_LOGIC;
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SIGNAL dat_en : STD_LOGIC;
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SIGNAL dat2_en : STD_LOGIC;
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SIGNAL credit : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
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SIGNAL credit_d : STD_LOGIC_VECTOR(5 DOWNTO 0);
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SIGNAL credit_e : STD_LOGIC;
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SIGNAL dat_full_d : STD_LOGIC;
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SIGNAL dat_full_i : STD_LOGIC;
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SIGNAL dat_empty_d : STD_LOGIC;
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SIGNAL dat_empty_i : STD_LOGIC;
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SIGNAL store_e : STD_LOGIC;
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SIGNAL store : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
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SIGNAL got_eop : STD_LOGIC;
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SIGNAL swallow_d : STD_LOGIC;
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SIGNAL swallow : STD_LOGIC;
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SIGNAL dat_dout_e : STD_LOGIC;
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SIGNAL dat_dout_d : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
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BEGIN
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---============================================---
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--== Reset for non-Connecting & non-Run logic ==--
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---============================================---
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rst_fct <= '1' WHEN (rst = '1') OR NOT((state = st_connecting) OR (state = st_run)) ELSE '0';
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---=====================---
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--== Synchronous Logic ==--
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---=====================---
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PROCESS (clk)
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF rst_fct = '0' THEN
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fct_full_i <= fct_full_d;
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IF credit_e = '1' THEN
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credit <= credit_d;
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END IF;
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ELSE
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credit <= (others => '0');
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fct_full_i <= '1';
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END IF;
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IF rst = '0' THEN
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swallow <= swallow_d;
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dat_full_i <= dat_full_d;
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dat_empty_i <= dat_empty_d;
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IF dat2_en = '1' THEN
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got_eop <= dat_din(datawidth);
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END IF;
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IF store_e = '1' THEN
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store <= dat_din;
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END IF;
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IF dat_dout_e = '1' THEN
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dat_dout <= dat_dout_d;
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END IF;
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ELSE
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got_eop <= '1';
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swallow <= '1';
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dat_full_i <= '1';
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dat_empty_i <= '1';
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store <= (others => '0');
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dat_dout <= (others => '0');
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END IF;
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END IF;
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END PROCESS;
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---====================---
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--== FCT Write Enable ==--
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---====================---
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fct_en <= NOT(fct_full_i) AND NOT(fct_nwrite);
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---========================---
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--== Data Out Read Enable ==--
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---========================---
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dat_en <= NOT(dat_empty_i) AND NOT(dat_nread);
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---========================---
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--== Data In Write Enable ==--
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---========================---
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dat2_en <= NOT(dat_full_i) AND NOT(dat_nwrite);
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---===========================---
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--== Transmit Credit Counter ==--
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---===========================---
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PROCESS(fct_en, dat_en, credit)
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VARIABLE tmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
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BEGIN
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tmp := fct_en & dat_en;
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CASE tmp IS
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WHEN "11" => credit_d <= credit + 7;
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WHEN "10" => credit_d <= credit + 8;
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WHEN "01" => credit_d <= credit - 1;
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WHEN OTHERS => credit_d <= credit;
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END CASE;
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END PROCESS;
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credit_e <= fct_en OR dat_en;
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---=======================---
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--== FCT Handshake Logic ==--
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---=======================---
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PROCESS(credit, fct_en)
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BEGIN
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IF (credit <= '1' & NOT(fct_en) & fct_en & "000") THEN
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fct_full_d <= '0';
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ELSE
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fct_full_d <= '1';
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END IF;
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END PROCESS;
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---========================---
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--== Packet swallow logic ==--
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---========================---
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PROCESS(state, swallow, dat_full_i, dat_nwrite, dat_din, got_eop)
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BEGIN
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IF (state /= st_Run) THEN
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swallow_d <= '1';
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ELSE
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IF (swallow = '1') THEN
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IF ((dat_full_i = '0') AND (dat_nwrite = '0') AND (dat_din(datawidth) = '1')) OR (got_eop = '1') THEN
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swallow_d <= '0';
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ELSE
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swallow_d <= '1';
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END IF;
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ELSE
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swallow_d <= '0';
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END IF;
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END IF;
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END PROCESS;
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---========================---
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--== FIFO full flag logic ==--
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---========================---
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PROCESS(state, swallow, got_eop, dat_full_i, dat_nwrite, dat_din, credit, dat_en, dat_empty_i, dat_nread)
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BEGIN
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IF (state /= st_Run) THEN
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dat_full_d <= '0';
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ELSE
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IF (swallow = '1') THEN
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IF (got_eop = '1') AND (dat_full_i = '0') AND (dat_nwrite = '0') AND (dat_din(datawidth) = '0') THEN
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dat_full_d <= '1';
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ELSE
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dat_full_d <= '0';
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END IF;
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ELSE
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IF (credit(5 DOWNTO 1) = "000000") AND ((credit(0) = '0') OR (dat_en = '1')) THEN
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dat_full_d <= dat_full_i OR NOT(dat_nwrite);
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ELSE
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dat_full_d <= NOT(dat_empty_i) AND dat_nread AND (dat_full_i OR NOT(dat_nwrite));
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END IF;
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END IF;
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END IF;
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END PROCESS;
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---=========================---
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--== FIFO empty flag logic ==--
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---=========================---
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PROCESS(state, swallow, credit, dat_en, dat_full_i, dat_nwrite, dat_empty_i, dat_nread)
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BEGIN
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IF (state /= st_Run) OR (swallow = '1') THEN
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dat_empty_d <= '1';
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ELSE
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IF (credit(5 DOWNTO 1) = "000000") AND ((credit(0) = '0') OR (dat_en = '1')) THEN
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dat_empty_d <= '1';
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ELSE
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dat_empty_d <= NOT(dat_full_i) AND dat_nwrite AND (dat_empty_i OR NOT(dat_nread));
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END IF;
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END IF;
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END PROCESS;
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---===============---
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--== FIFO memory ==--
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---===============---
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store_e <= NOT(dat_full_i);
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---=======================---
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--== FIFO data out logic ==--
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---=======================---
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PROCESS(dat_full_i, dat_din, store)
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BEGIN
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CASE dat_full_i IS
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WHEN '0' => dat_dout_d <= dat_din;
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WHEN '1' => dat_dout_d <= store;
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WHEN OTHERS => NULL;
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END CASE;
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END PROCESS;
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dat_dout_e <= '1' WHEN (dat_empty_i = '1') OR (dat_nread = '0') ELSE '0';
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---======================================---
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--== Shared Internal & External Signals ==--
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---======================================---
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dat_full <= dat_full_i;
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fct_full <= fct_full_i;
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dat_empty <= dat_empty_i;
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END rtl;
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