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---====================== Start Software License ========================---
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--== ==--
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--== This license governs the use of this software, and your use of ==--
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--== this software constitutes acceptance of this license. Agreement ==--
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--== with all points is required to use this software. ==--
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--== ==--
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--== 1. This source file may be used and distributed without ==--
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--== restriction provided that this software license statement is not ==--
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--== removed from the file and that any derivative work contains the ==--
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--== original software license notice and the associated disclaimer. ==--
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--== ==--
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--== 2. This source file is free software; you can redistribute it ==--
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--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==--
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--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==--
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--== This implies modification and/or derivative work of this Software. ==--
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--== ==--
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--== 3. This source is distributed in the hope that it will be useful, ==--
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--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==--
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--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==--
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--== ==--
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--== Your rights under this license are terminated immediately if you ==--
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--== breach it in any way. ==--
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--== ==--
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---======================= End Software License =========================---
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---====================== Start Copyright Notice ========================---
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--== ==--
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--== Filename ..... transmitter.vhd ==--
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--== Download ..... http://www.ida.ing.tu-bs.de ==--
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--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
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--== Authors ...... Björn Osterloh, Karel Kotarowski ==--
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--== Contact ...... Björn Osterloh (b.osterloh@tu-bs.de) ==--
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--== Copyright .... Copyright (c) 2008 IDA ==--
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--== Project ...... SoCWire CODEC ==--
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--== Version ...... 1.00 ==--
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--== Conception ... 11 November 2008 ==--
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--== Modified ..... N/A ==--
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--== ==--
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---======================= End Copyright Notice =========================---
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE WORK.ALL;
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ENTITY transmitter IS
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GENERIC(
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datawidth : NATURAL RANGE 8 TO 8192
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);
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PORT(
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--== General Interface (Sync Rst, 50MHz Clock) ==--
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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--== SoCWire Interface ==--
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state : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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--== External Transmit Interface ==--
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tx : OUT STD_LOGIC_VECTOR(datawidth+1 DOWNTO 0);
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tx_valid : OUT STD_LOGIC;
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--== Data Input Interface ==--
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dat_full : OUT STD_LOGIC;
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dat_nwrite : IN STD_LOGIC;
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dat_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
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--== FCT Input Interface ==--
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fct_full : OUT STD_LOGIC;
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fct_nwrite : IN STD_LOGIC
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);
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END transmitter;
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ARCHITECTURE rtl OF transmitter IS
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---==========================---
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--== Constants Declarations ==--
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---==========================---
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CONSTANT st_error_reset : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
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CONSTANT st_error_wait : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
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CONSTANT st_ready : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
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CONSTANT st_started : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
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CONSTANT st_connecting : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
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CONSTANT st_run : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101";
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CONSTANT st_unknown_1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "110";
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CONSTANT st_unknown_2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
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CONSTANT zeros : STD_LOGIC_VECTOR(datawidth DOWNTO 5) := (others => '0');
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---=======================---
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--== Signal Declarations ==--
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---=======================---
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SIGNAL tx_rst : STD_LOGIC;
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SIGNAL clk_en : STD_LOGIC;
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SIGNAL load_d : STD_LOGIC;
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SIGNAL load : STD_LOGIC;
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SIGNAL bit_array_d : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
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SIGNAL bit_array : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
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SIGNAL parity_d : STD_LOGIC;
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SIGNAL parity : STD_LOGIC;
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SIGNAL fct_en : STD_LOGIC;
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SIGNAL dat_en : STD_LOGIC;
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SIGNAL fct_full_i : STD_LOGIC;
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SIGNAL dat_full_i : STD_LOGIC;
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BEGIN
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---=========================================================---
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--== Generate Tx Reset Signal to hold Transmitter in Reset ==--
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---=========================================================---
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tx_rst <= '1' WHEN ((state /= st_Started) AND (state /= st_connecting) AND
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(state /= st_run)) OR (rst = '1') ELSE '0';
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---=====================---
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--== Synchronous Logic ==--
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---=====================---
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PROCESS (clk)
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF tx_rst = '0' THEN
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clk_en <= NOT clk_en;
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load <= load_d;
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IF load = '1' THEN
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parity <= parity_d;
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bit_array <= bit_array_d;
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END IF;
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ELSE
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clk_en <= '0';
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load <= '0';
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parity <= '1';
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bit_array <= (others => '0');
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END IF;
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END IF;
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END PROCESS;
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---===========================================================---
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--== Generate pulse for cycle where shift register is loaded ==--
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---===========================================================---
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load_d <= NOT tx_rst;
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---===========================================================---
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--== FCT & NChar Input Interfaces (pre-sniff then handshake) ==--
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---===========================================================---
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PROCESS(load_d, state, fct_nwrite, dat_nwrite)
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BEGIN
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IF (load_d = '1') THEN
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IF ((state = st_connecting) OR (state = st_run)) AND (fct_nwrite = '0') THEN
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fct_full_i <= '0';
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dat_full_i <= '1';
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ELSIF (state = st_run) AND (dat_nwrite = '0') THEN
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fct_full_i <= '1';
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dat_full_i <= '0';
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ELSE
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fct_full_i <= '1';
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dat_full_i <= '1';
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END IF;
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ELSE
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fct_full_i <= '1';
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dat_full_i <= '1';
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END IF;
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END PROCESS;
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fct_en <= NOT(fct_full_i) AND NOT(fct_nwrite);
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dat_en <= NOT(dat_full_i) AND NOT(dat_nwrite);
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---==================================---
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--== Character Priority Multiplexor ==--
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---==================================---
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PROCESS(load, bit_array, fct_en, dat_en, parity, dat_din)
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BEGIN
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IF (load = '1') THEN
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IF (fct_en = '1') THEN
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bit_array_d <= zeros & "00001";
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ELSIF (dat_en = '1') THEN
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IF (dat_din(datawidth) = '1') THEN
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bit_array_d <= zeros & "00" & NOT(dat_din(0)) & dat_din(0) & '1';
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ELSE
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bit_array_d <= dat_din(datawidth-1 DOWNTO 0) & '0';
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END IF;
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ELSE
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bit_array_d <= zeros & "10111";
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END IF;
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ELSE
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bit_array_d <= (others => '0');
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END IF;
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END PROCESS;
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PROCESS(bit_array_d, bit_array)
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VARIABLE temp : STD_LOGIC;
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BEGIN
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temp := '0' XOR bit_array_d(0);
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FOR i IN 1 TO datawidth LOOP
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temp := temp XOR bit_array(i);
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END LOOP;
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parity_d <= NOT temp;
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END PROCESS;
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---===================================---
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--== Drive Tx Data Output (NONE-TMR) ==--
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---===================================---
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tx <= bit_array & parity;
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tx_valid <= load;
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---======================================---
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--== Shared Internal & External Signals ==--
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---======================================---
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fct_full <= fct_full_i;
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dat_full <= dat_full_i;
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END rtl;
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