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---====================== Start Software License ========================---
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--== ==--
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--== This license governs the use of this software, and your use of ==--
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--== this software constitutes acceptance of this license. Agreement ==--
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--== with all points is required to use this software. ==--
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--== ==--
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--== 1. This source file may be used and distributed without ==--
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--== restriction provided that this software license statement is not ==--
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--== removed from the file and that any derivative work contains the ==--
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--== original software license notice and the associated disclaimer. ==--
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--== ==--
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--== 2. This source file is free software; you can redistribute it ==--
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--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==--
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--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==--
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--== This implies modification and/or derivative work of this Software. ==--
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--== ==--
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--== 3. This source is distributed in the hope that it will be useful, ==--
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--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==--
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--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==--
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--== ==--
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--== Your rights under this license are terminated immediately if you ==--
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--== breach it in any way. ==--
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--== ==--
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---======================= End Software License =========================---
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---====================== Start Copyright Notice ========================---
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--== ==--
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--== Filename ..... entrance.vhd ==--
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--== Download ..... http://www.ida.ing.tu-bs.de ==--
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--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
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--== Authors ...... Björn Osterloh, Karel Kotarowski ==--
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--== Contact ...... Björn Osterloh (b.osterloh@tu-bs.de) ==--
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--== Copyright .... Copyright (c) 2008 IDA ==--
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--== Project ...... SoCWire Switch ==--
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--== Version ...... 1.00 ==--
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--== Conception ... 11 November 2008 ==--
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--== Modified ..... N/A ==--
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--== ==--
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---======================= End Copyright Notice =========================---
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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ENTITY entrance IS
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GENERIC(
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--== Number Of Ports ==--
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datawidth : NATURAL RANGE 8 TO 8192;
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nports : NATURAL RANGE 2 TO 32
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);
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PORT(
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--== General Interface ==--
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clk : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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--== Input Interface ==--
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nwrite : IN STD_LOGIC;
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full : OUT STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
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--== Connection Interface ==--
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full_in : IN STD_LOGIC;
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connect : OUT STD_LOGIC;
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wanted : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0)
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);
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END entrance;
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ARCHITECTURE rtl OF entrance IS
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---=========================---
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--== Function Declarations ==--
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---=========================---
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FUNCTION ports2bus(nports : NATURAL RANGE 2 TO 32) RETURN NATURAL IS
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BEGIN
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CASE nports IS
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WHEN 2 => RETURN 1;
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WHEN 3 TO 4 => RETURN 2;
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WHEN 5 TO 8 => RETURN 3;
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WHEN 9 TO 16 => RETURN 4;
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WHEN 17 TO 32 => RETURN 5;
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END CASE;
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END ports2bus;
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---=====================---
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--== Type Declarations ==--
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---=====================---
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TYPE states IS
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(wait4hdr,
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transfer
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);
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---=======================---
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--== Signal Declarations ==--
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---=======================---
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SIGNAL state : states;
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SIGNAL ditch_data : STD_LOGIC;
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SIGNAL hw_addr : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
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SIGNAL wanted_int : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
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SIGNAL full_i : STD_LOGIC;
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BEGIN
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---===========================---
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--== Create Hardware Address ==--
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---===========================---
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G0 : FOR i IN 0 TO nports-1 GENERATE
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hw_addr(i) <= '1' WHEN (din(ports2bus(nports)-1 DOWNTO 0) = i) ELSE '0';
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END GENERATE G0;
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---================================---
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--== Desired connection selection ==--
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---================================---
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wanted_int <= hw_addr WHEN (state = wait4hdr) ELSE (others => '0');
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---============================---
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--== Desired connection logic ==--
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---============================---
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PROCESS(clk)
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF (rst = '1') THEN
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wanted <= (OTHERS => '0');
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ELSIF (state = wait4hdr) THEN
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wanted <= wanted_int;
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END IF;
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END IF;
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END PROCESS;
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---=================---
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--== State Machine ==--
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---=================---
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PROCESS(clk)
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF (rst = '1') THEN
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state <= wait4hdr;
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ditch_data <= '0';
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connect <= '0';
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ELSE
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CASE state IS
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WHEN wait4hdr =>
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IF (nwrite = '0') THEN
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ditch_data <= '1';
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connect <= '1';
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state <= transfer;
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END IF;
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WHEN transfer =>
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ditch_data <= '0';
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IF (nwrite = '0') AND (full_i = '0') AND (din(datawidth) = '1') THEN
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connect <= '0';
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state <= wait4hdr;
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END IF;
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END CASE;
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END IF;
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END IF;
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END PROCESS;
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---========================---
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--== Drive output signals ==--
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---========================---
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full_i <= '0' WHEN (ditch_data = '1') OR (full_in = '0') ELSE '1';
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full <= full_i;
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END rtl;
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