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---====================== Start Copyright Notice ========================---
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--== ==--
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--== Filename ..... codec_tb.vhd ==--
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--== Download ..... http://www.ida.ing.tu-bs.de ==--
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--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
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--== Authors ...... Björn Osterloh, Karel Kotarowski ==--
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--== Contact ...... Björn Osterloh (b.osterloh@tu-bs.de) ==--
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--== Copyright .... Copyright (c) 2008 IDA ==--
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--== Project ...... SoCWire CODEC Testbench ==--
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--== Version ...... 1.00 ==--
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--== Conception ... 22 April 2009 ==--
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--== Modified ..... N/A ==--
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--== ==--
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---======================= End Copyright Notice =========================---
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---====================== CODEC Loopback Testbench ======================---
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--== 1 SoCWire CODEC with 8 Bit data word width is operated in Loobpack
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--== mode. Packets from 1 Byte to 64KByte length increased by 1 Byte
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--== are send over the link. Each packet is terminated with EOP marker.
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--== The packets are compared and errors reported.
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--== The active signal is monitored to report link errors.
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--========================================================================--
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.std_logic_textio.all;
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USE STD.TEXTIO.all;
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ENTITY CODEC_Loopback_tb_vhd IS
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GENERIC (
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--== USE GEREIC MAPPING FROM TOPLEVEL!!! ==--
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datawidth : NATURAL RANGE 8 TO 8192:=8;
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speed : NATURAL RANGE 1 TO 100:=10; -- Set CODEC speed to system clock in nanoseconds !
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after64 : NATURAL RANGE 1 TO 6400:=64; -- Spacewire Standard 6400 = 6.4 us
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after128 : NATURAL RANGE 1 TO 12800:=128; -- Spacewire Standard 12800 = 12.8 us
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disconnect_detection : NATURAL RANGE 1 TO 850:=85 -- Spacewire Standard 850 = 850 ns
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);
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END CODEC_Loopback_tb_vhd;
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ARCHITECTURE behavior OF CODEC_Loopback_tb_vhd IS
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COMPONENT socwire_codec
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GENERIC(
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--== USE GEREIC MAPPING FROM TOPLEVEL!!!==--
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datawidth : NATURAL RANGE 8 TO 8192:=8;
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speed : NATURAL RANGE 1 TO 100:=10; -- Set CODEC speed to system clock in nanoseconds !
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after64 : NATURAL RANGE 1 TO 6400:=64; -- Spacewire Standard 6400 = 6.4 us
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after128 : NATURAL RANGE 1 TO 12800:=128; -- Spacewire Standard 12800 = 12.8 us
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disconnect_detection : NATURAL RANGE 1 TO 850:=85 -- Spacewire Standard 850 = 850 ns
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);
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PORT(
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rst : IN std_logic;
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clk : IN std_logic;
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socw_en : IN std_logic;
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socw_dis : IN std_logic;
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rx : IN std_logic_vector(9 downto 0);
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rx_valid : IN std_logic;
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dat_nwrite : IN std_logic;
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dat_din : IN std_logic_vector(8 downto 0);
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dat_nread : IN std_logic;
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tx : OUT std_logic_vector(9 downto 0);
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tx_valid : OUT std_logic;
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dat_full : OUT std_logic;
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dat_empty : OUT std_logic;
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dat_dout : OUT std_logic_vector(8 downto 0);
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active : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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SIGNAL rst : std_logic := '0';
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SIGNAL clk : std_logic := '0';
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SIGNAL socw_en : std_logic := '0';
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SIGNAL socw_dis : std_logic := '0';
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SIGNAL rx_valid : std_logic := '0';
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SIGNAL dat_nwrite : std_logic := '0';
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SIGNAL dat_nread : std_logic := '0';
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SIGNAL rx : std_logic_vector(9 downto 0) := (others=>'0');
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SIGNAL dat_din : std_logic_vector(8 downto 0) := (others=>'0');
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--Outputs
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SIGNAL tx : std_logic_vector(9 downto 0);
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SIGNAL tx_valid : std_logic;
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SIGNAL dat_full : std_logic;
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SIGNAL dat_empty : std_logic;
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SIGNAL dat_dout : std_logic_vector(8 downto 0);
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SIGNAL active : std_logic;
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--Testbench
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constant clk_per : time := 10 ns; -- 10 ns -> 100 MHz clock
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signal clk_cnt : integer := 0; -- clock counter
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signal dat_cnt : integer := 0; -- data counter
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signal flag : std_logic:='0';
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signal data_gen : std_logic_vector (8 downto 0);
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signal data8bit : std_logic_vector (7 downto 0):=(others=>'0');
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signal dat_len : integer :=0;
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signal loop_cnt : integer := 0;
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signal compare_cnt : std_logic_vector ( 7 downto 0):="00000001";
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signal monitoractive : std_logic:='0';
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Signal StartDatGen : std_logic:='0';
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Signal EndDatGen: std_logic;
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BEGIN
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uut: socwire_codec
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GENERIC MAP (
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datawidth =>datawidth,
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speed =>speed,
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after64 =>after64,
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after128 =>after128,
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disconnect_detection =>disconnect_detection)
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PORT MAP(
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rst => rst,
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clk => clk,
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socw_en => socw_en,
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socw_dis => socw_dis,
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rx => rx,
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rx_valid => rx_valid,
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tx => rx,
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tx_valid => rx_valid,
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dat_full => dat_full,
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dat_nwrite => dat_nwrite,
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dat_din => dat_din,
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dat_nread => dat_nread,
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dat_empty => dat_empty,
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dat_dout => dat_dout,
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active => active
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);
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-- clock generation
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clk_gen : process
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begin
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wait for clk_per / 2;
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clk <= not clk;
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end process;
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-- read data
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read_core: process(clk,dat_empty)
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begin
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If clk ='1' and clk'event then
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If dat_empty = '0' and active = '1' then
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dat_nread<='0';
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else
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dat_nread<='1';
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end if;
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end if;
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end process;
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-- Compare data
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compare_core: Process (clk,dat_nread)
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Begin
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If CLK = '1' and CLK'event then
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If dat_nread = '0' and dat_empty = '0' then
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If dat_dout = 256 then
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compare_cnt<="00000001";
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elsif dat_dout <= 255 then
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If compare_cnt = dat_dout (7 downto 0) then
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compare_cnt<=compare_cnt + '1';
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else
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ASSERT False
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Report "Data Error"
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Severity Failure;
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end if;
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end if;
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end if;
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end if;
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end process;
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-- clock counter
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clk_counter : process(clk)
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begin
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if CLK ='0' and CLK'event then
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clk_cnt <= clk_cnt + 1;
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end if;
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end process;
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-- generate reset
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ctrl_sig_gen : process (clk, clk_cnt)
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begin
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If CLK='1' and CLK'event then
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case clk_cnt is
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when 1 => rst <= '1';
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when 10 => rst <= '0';
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when others => null;
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end case;
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end if;
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end process;
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-- data generation
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data_gen_p: Process (clk,rst,active,clk_cnt,dat_cnt,StartDatGen)
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begin
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If rst = '1' then
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data_gen<="000000000";
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dat_nwrite<='1';
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dat_cnt<= 0;
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EndDatGen<='0';
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data8bit<="00000001";
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elsif Clk = '1' and clk'event then
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If active = '1' and dat_full = '0' and StartDatGen ='1' then
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EndDatGen<='0';
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dat_cnt<=dat_cnt + 1;
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If dat_cnt >= 1 and dat_cnt < dat_len then
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dat_nwrite<='0';
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data8Bit<=data8bit +'1';
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dat_din<='0' & data8bit;
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elsif dat_cnt = dat_len then
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dat_din<="100000000";
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elsif dat_cnt = dat_len+1 then
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dat_nwrite<='1';
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dat_cnt<= 0 ;
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EndDatGen<= '1';
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data_gen<="000000000";
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data8bit<="00000001";
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end if;
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end if;
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end if;
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end process;
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-- observe active
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Process ( monitoractive,active)
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Begin
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If monitoractive = '1' then
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If active = '0' then
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ASSERT False
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Report "Link Error"
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Severity Failure;
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end if;
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end if;
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end Process;
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tb : PROCESS
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BEGIN
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StartDatGen<='0';
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dat_len <=1;
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socw_en<='1';
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wait until active = '1';
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wait for 2 us;
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StartDatGen<='1';
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monitoractive<='1';
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wait until EndDatGen = '1';
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StartDatGen<='0';
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wait for 200 ns;
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-- up to 64 KByte Packet length
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for index IN 0 to 65536 LOOP
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loop_cnt<=index;
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dat_len <=dat_len +1;
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StartDatGen<='1';
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wait until EndDatGen = '1';
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StartDatGen<='0';
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wait for 500 ns;
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END LOOP;
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wait for 5 us;
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ASSERT False
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Report "End of Test "
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Severity Failure;
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END PROCESS;
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END;
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No newline at end of file
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No newline at end of file
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