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---====================== Start Copyright Notice ========================---
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--== ==--
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--== Filename ..... switch_tb.vhd ==--
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--== Download ..... http://www.ida.ing.tu-bs.de ==--
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--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
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--== Authors ...... Björn Osterloh ==--
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--== Contact ...... Björn Osterloh (b.osterloh@tu-bs.de) ==--
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--== Copyright .... Copyright (c) 2008 IDA ==--
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--== Project ...... SoCWire Switch Testbench ==--
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--== Version ...... 1.00 ==--
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--== Conception ... 22 April 2009 ==--
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--== Modified ..... N/A ==--
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--== ==--
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---======================= End Copyright Notice =========================---
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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USE WORK.ALL;
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ENTITY switch_tb IS
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GENERIC(
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--== Number Of Ports ==--
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nports : NATURAL RANGE 2 TO 32 := 4;
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--== Set Codec Speed to system clock in nanoseconds! ==--
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--== DO NOT CHANGE THE GENERICS IN THE SUB MODULES!! ==--
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datawidth : NATURAL RANGE 8 TO 8192:=8;
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speed : NATURAL RANGE 1 TO 100:=10; -- Set CODEC speed to system clock in nanoseconds !
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after64 : NATURAL RANGE 1 TO 6400:=64; -- Spacewire Standard 6400 = 6.4 us
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after128 : NATURAL RANGE 1 TO 12800:=128; -- Spacewire Standard 12800 = 12.8 us
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disconnect_detection : NATURAL RANGE 1 TO 850:=85 -- Spacewire Standard 850 = 850 ns
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);
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END switch_tb;
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ARCHITECTURE behavior OF switch_tb IS
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COMPONENT socwire_switch IS
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GENERIC(
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datawidth : NATURAL RANGE 8 TO 8192;
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nports : NATURAL RANGE 2 TO 32;
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speed : NATURAL RANGE 1 TO 100
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);
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PORT(
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--== General Interface (Sync Rst, 50MHz Clock) ==--
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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--== Serial Receive Interface ==--
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rx : IN STD_LOGIC_VECTOR((datawidth+2)*nports-1 DOWNTO 0);
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rx_valid : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
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--== Serial Transmit Interface ==--
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tx : OUT STD_LOGIC_VECTOR((datawidth+2)*nports-1 DOWNTO 0);
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tx_valid : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
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--== Active Interface ==--
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active : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT socwire_codec
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GENERIC(
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datawidth : NATURAL RANGE 8 TO 8192;
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speed : NATURAL RANGE 1 TO 100;
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after64 : NATURAL RANGE 1 TO 6400;
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after128 : NATURAL RANGE 1 TO 12800;
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disconnect_detection : NATURAL RANGE 1 TO 850
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);
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PORT(
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rst : IN std_logic;
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clk : IN std_logic;
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socw_en : IN std_logic;
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socw_dis : IN std_logic;
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rx : IN std_logic_vector(datawidth+1 downto 0);
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rx_valid : IN std_logic;
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dat_nwrite : IN std_logic;
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dat_din : IN std_logic_vector(datawidth downto 0);
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dat_nread : IN std_logic;
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tx : OUT std_logic_vector(datawidth+1 downto 0);
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tx_valid : OUT std_logic;
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dat_full : OUT std_logic;
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dat_empty : OUT std_logic;
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dat_dout : OUT std_logic_vector(datawidth downto 0);
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active : OUT std_logic
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);
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END COMPONENT;
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SIGNAL rst : STD_LOGIC;
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SIGNAL clk : STD_LOGIC:= '0';
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SIGNAL rx : STD_LOGIC_VECTOR((datawidth+2)*nports-1 DOWNTO 0);
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SIGNAL rx_valid : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
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SIGNAL tx : STD_LOGIC_VECTOR((datawidth+2)*nports-1 DOWNTO 0);
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SIGNAL tx_valid : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
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SIGNAL active_i : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
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SIGNAL active_ii : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
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SIGNAL socw_en : STD_LOGIC;
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SIGNAL socw_dis : STD_LOGIC;
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SIGNAL dat_full : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
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SIGNAL dat_nwrite : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
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SIGNAL dat_din : STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0);
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SIGNAL dat_nread : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
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SIGNAL dat_empty : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
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SIGNAL dat_dout : STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0);
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SIGNAL dat_nwrite_P0 : STD_LOGIC;
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SIGNAL dat_nwrite_P1 : STD_LOGIC;
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SIGNAL dat_nwrite_P2 : STD_LOGIC;
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SIGNAL dat_nwrite_P3 : STD_LOGIC;
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SIGNAL dat_din_P0 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_din_P1 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_din_P2 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_din_P3 : STD_LOGIC_VECTOR (datawidth downto 0);
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BEGIN
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-- Component Declaration for the Unit Under Test (UUT)
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U0 : socwire_switch
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GENERIC MAP
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(
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datawidth =>datawidth,
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nports => nports,
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speed => speed
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)
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PORT MAP
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(--== General Interface (Sync Rst) ==--
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clk => clk,
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rst => rst,
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rx => tx,
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rx_valid => tx_valid,
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tx => rx,
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tx_valid => rx_valid,
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active => active_i
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);
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G0 : FOR i IN 0 TO nports-1 GENERATE
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U1 : socwire_codec
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GENERIC MAP
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(
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datawidth =>datawidth,
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speed =>speed,
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after64 =>after64,
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after128 =>after128,
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disconnect_detection =>disconnect_detection
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)
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PORT MAP
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(--== General Interface (Sync Rst, 50MHz Clock) ==--
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rst => rst,
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clk => clk,
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--== Link Enable Interface ==--
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socw_en => socw_en,
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socw_dis => socw_dis,
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--== Serial Receive Interface ==--
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rx => rx((i+1)*10-1 DOWNTO i*10),
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rx_valid => rx_valid(i),
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--== Serial Transmit Interface ==--
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tx => tx((i+1)*10-1 DOWNTO i*10),
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tx_valid => tx_valid(i),
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--== Data Input Interface ==--
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dat_full => dat_full(i),
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dat_nwrite => dat_nwrite(i),
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dat_din => dat_din((i+1)*9-1 DOWNTO i*9),
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--== Data Output Interface ==--
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dat_nread => dat_nread(i),
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dat_empty => dat_empty(i),
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dat_dout => dat_dout((i+1)*9-1 DOWNTO i*9),
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--== Active Interface ==--
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active => active_ii(i)
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);
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END GENERATE G0;
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socw_en <= '1';
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socw_dis <= '0';
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clk <= not clk after 5 ns;
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dat_nwrite(0)<=dat_nwrite_P0;
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dat_nwrite(1)<=dat_nwrite_P1;
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dat_nwrite(2)<=dat_nwrite_P2;
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dat_nwrite(3)<=dat_nwrite_P3;
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dat_din(8 downto 0) <=dat_din_P0;
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dat_din(17 downto 9) <=dat_din_P1;
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dat_din(26 downto 18)<=dat_din_P2;
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dat_din(35 downto 27)<=dat_din_P3;
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tb : PROCESS
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BEGIN
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rst <= '1';
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dat_nwrite_P0<='1';
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dat_nwrite_P1<='1';
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dat_nwrite_P2<='1';
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dat_nwrite_P3<='1';
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dat_din_P0<=(others=>'0');
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dat_din_P1<=(others=>'0');
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dat_din_P2<=(others=>'0');
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dat_din_P3<=(others=>'0');
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dat_nread <= (others => '1');
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wait for 100 ns;
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rst <= '0';
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wait for 1 us;
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dat_nread <= (others => '0');
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-- Send Packet from Port 0 to Port 1
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dat_nwrite_P0<='0';
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dat_din_P0<="000000001"; -- Port 1
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wait for 10 ns;
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dat_din_P0<="000001010"; -- Data 0
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wait for 10 ns;
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dat_din_P0<="000001011"; -- Data 1
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wait for 10 ns;
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dat_din_P0<="100000000"; -- EOP
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wait for 10 ns;
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dat_nwrite_P0<='1';
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-- Send Packet from Port 2 to Port 3
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dat_nwrite_P2<='0';
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dat_din_P2<="000000011"; -- Port 3
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wait for 10 ns;
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dat_din_P2<="000001100"; -- Data 0
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wait for 10 ns;
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dat_din_P2<="000001101"; -- Data 1
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wait for 10 ns;
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dat_din_P2<="100000000"; -- EOP
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wait for 10 ns;
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dat_nwrite_P2<='1';
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-- Send Packet from Port 0 and Port 1 to Port 2 and Port 3
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dat_nwrite_P0<='0';
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dat_din_P0<="000000010"; -- Port 2
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dat_nwrite_P1<='0';
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dat_din_P1<="000000011"; -- Port 3
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wait for 10 ns;
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dat_din_P0<="000001110"; -- Data 0
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dat_din_P1<="000001010"; -- Data 0
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wait for 10 ns;
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dat_din_P0<="000001111"; -- Data 1
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dat_din_P1<="000001011"; -- Data 1
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wait for 10 ns;
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dat_din_P0<="100000000"; -- EOP
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dat_din_P1<="100000000"; -- EOP
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wait for 10 ns;
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dat_nwrite_P0<='1';
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dat_nwrite_P1<='1';
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wait for 1000 ms; --wait very long
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END PROCESS;
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END;
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