| Line 7... |
Line 7... |
--== Contact ...... Björn Osterloh (b.osterloh@tu-bs.de) ==--
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--== Contact ...... Björn Osterloh (b.osterloh@tu-bs.de) ==--
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--== Copyright .... Copyright (c) 2008 IDA ==--
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--== Copyright .... Copyright (c) 2008 IDA ==--
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--== Project ...... SoCWire Switch Testbench ==--
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--== Project ...... SoCWire Switch Testbench ==--
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--== Version ...... 1.00 ==--
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--== Version ...... 1.00 ==--
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--== Conception ... 22 April 2009 ==--
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--== Conception ... 22 April 2009 ==--
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--== Modified ..... N/A ==--
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--== Modified ..... holgerm : minor bug fix marked with holgerm ==--
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--== ==--
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--== ==--
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---======================= End Copyright Notice =========================---
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---======================= End Copyright Notice =========================---
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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| Line 39... |
Line 39... |
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COMPONENT socwire_switch IS
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COMPONENT socwire_switch IS
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GENERIC(
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GENERIC(
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datawidth : NATURAL RANGE 8 TO 8192;
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datawidth : NATURAL RANGE 8 TO 8192;
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nports : NATURAL RANGE 2 TO 32;
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nports : NATURAL RANGE 2 TO 32;
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speed : NATURAL RANGE 1 TO 100
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speed : NATURAL RANGE 1 TO 100;
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-- holgerm
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after64 : NATURAL RANGE 1 TO 6400:=6400; -- Spacewire Standard 6400 = 6.4 us
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after128 : NATURAL RANGE 1 TO 12800:=12800; -- Spacewire Standard 12800 = 12.8 us
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disconnect_detection : NATURAL RANGE 1 TO 850:=850 -- Spacewire Standard 850 = 850 ns
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-- holgerm
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);
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);
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PORT(
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PORT(
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--== General Interface (Sync Rst, 50MHz Clock) ==--
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--== General Interface (Sync Rst, 50MHz Clock) ==--
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rst : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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| Line 124... |
Line 129... |
SIGNAL dat_din_P0 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_din_P0 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_din_P1 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_din_P1 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_din_P2 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_din_P2 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_din_P3 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_din_P3 : STD_LOGIC_VECTOR (datawidth downto 0);
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-- holgerm
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-- compile with "vsim -novopt switch_tb" otherwise optimization will delete these signals
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SIGNAL dat_empty_P0 : STD_LOGIC;
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SIGNAL dat_empty_P1 : STD_LOGIC;
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SIGNAL dat_empty_P2 : STD_LOGIC;
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SIGNAL dat_empty_P3 : STD_LOGIC;
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SIGNAL dat_dout_P0 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_dout_P1 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_dout_P2 : STD_LOGIC_VECTOR (datawidth downto 0);
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SIGNAL dat_dout_P3 : STD_LOGIC_VECTOR (datawidth downto 0);
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-- holgerm
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BEGIN
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BEGIN
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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U0 : socwire_switch
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U0 : socwire_switch
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GENERIC MAP
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GENERIC MAP
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(
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(
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datawidth =>datawidth,
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datawidth =>datawidth,
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nports => nports,
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nports => nports,
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speed => speed
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speed => speed,
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-- holgerm
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after64 =>after64,
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after128 =>after128,
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disconnect_detection =>disconnect_detection
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-- holgerm
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)
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)
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PORT MAP
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PORT MAP
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(--== General Interface (Sync Rst) ==--
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(--== General Interface (Sync Rst) ==--
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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| Line 199... |
Line 219... |
dat_din(8 downto 0) <=dat_din_P0;
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dat_din(8 downto 0) <=dat_din_P0;
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dat_din(17 downto 9) <=dat_din_P1;
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dat_din(17 downto 9) <=dat_din_P1;
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dat_din(26 downto 18)<=dat_din_P2;
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dat_din(26 downto 18)<=dat_din_P2;
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dat_din(35 downto 27)<=dat_din_P3;
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dat_din(35 downto 27)<=dat_din_P3;
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-- holgerm
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-- compile with "vsim -novopt switch_tb" otherwise optimization will delete these signals
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dat_empty_P0 <= dat_empty(0);
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dat_empty_P1 <= dat_empty(1);
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dat_empty_P2 <= dat_empty(2);
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dat_empty_P3 <= dat_empty(3);
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dat_dout_P0 <= dat_dout(8 downto 0);
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dat_dout_P1 <= dat_dout(17 downto 9);
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dat_dout_P2 <= dat_dout(26 downto 18);
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dat_dout_P3 <= dat_dout(35 downto 27);
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-- holgerm
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tb : PROCESS
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tb : PROCESS
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BEGIN
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BEGIN
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