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/* Because minimum latency is a key issue, the fifo empty flag is monitored and
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//File name=Module=Cfg_Ctrl 2005-04-03 btltz@mail.china.com btltz from CASIC
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data transferred whenever the buffer has data.
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//Description: Transact commands.
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*/
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// Include "control logic", "control/status register(and the gpio output pins)",
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// "configuration port". Note routing tables is in "LSer".
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module Cfg_Ctrl #(parameter DW=32,AW=32)
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//Origin: SpaceWire Std - Draft-1(Clause 9/10) of ECSS(European Cooperation for Space Standardization),ESTEC,ESA.
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(// configuration interface(CFG) for user to inspect
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// SpaceWire Router Requirements Specification Issue 1 Rev 5. Astrium & University of Dundee
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output[DW-1:0] cfg_data_o,
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//-- TODO: make the rtl faster
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//
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/*synthesize translate_off*/
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`include "timescale.v"
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/*synthesize translate_on */
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`define reset 1 // WISHBONE standard reset
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`define XIL_BRAM // Use Xilinx block RAM
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`define XIL_DISRAM // Use Xilinx distributed RAM
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`define TOOL_NOTSUP_PORT_ARRAY // If the tools not support port array declaration
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module Cfg_Ctrl #(parameter DW=32,AW=32, IO_PORTNUM=16, CFG_AW=4, IO_DW=10, EXT_DW=9)
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(
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// interface with SpW I/O ports, External port
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output [PORTNUM-1:0] rd_IBUF_o, // Note write to SpW IO port FIFO is performed by "switch core"
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`ifdef TOOL_NOTSUP_PORT_ARRAY
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input [IO_DW-1:0] SpW_D0_i, SpW_D1_i, SpW_D2_i, SpW_D3_i,
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SpW_D4_i, SpW_D5_i, SpW_D6_i, SpW_D7_i,
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SpW_D8_i, SpW_D9_i, SpW_D10_i,SpW_D11_i,
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SpW_D12_i,SpW_D13_i,SpW_D14_i,SpW_D15_i,
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`else
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input [IO_DW-1:0] SpW_D_i [0:PORTNUM-1],
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`endif
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input [PORTNUM-1:0] empty_IBUF_i, // empty flag of SpW input interface buffer(fifo)
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input [PORTNUM-1:0] full_OBUF_i, // full flag of SpW output interface buffer(fifo)
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output [EXT_DW-1:0] EXT_data_o,
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output we_EXTport_o,
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output rd_EXTport_o,
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input [EXT_DW-1:0] EXT_data_i,
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input empty_eibuf_i, // empty flag of external input port buffer(fifo)
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input full_eobuf_i, // full flag of external output port buffer(fifo)
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// interface for user to inspect
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output cfg_int_o, // interrupt the user application
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output cfg_int_o, // interrupt the user application
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output cfg_wrbusy_o, // configuration write in progress
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output cfg_wrbusy_o, // configuration write in progress
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output[AW-1:0] cfg_int_addr,
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output[AW-1:0] cfg_int_addr,
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input [AW-1:0] cfg_addr_i,
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input [AW-1:0] cfg_addr_i,
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//input [DW-1:0] cfg_data_i, //reserved
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//input [DW-1:0] cfg_data_i, //reserved
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//input [] cfg_ben_i, //configuration byte enable
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//input [] cfg_ben_i, //configuration byte enable
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//input cfg_wren_i, //reserved
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//input cfg_wren_i, //reserved
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);
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//N-Chars from one packet shall not be interleaved with N-Chars from another packet(but FCTs,NULL,TimeCodes).
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//When EOP marker seen, router terminates connection and frees output port
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//An EEP received by a routing switch shall be transferred through the routing switch in the same way as an EOP
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//The first data character following either EOP or EEP shall be taken as the first character of the next packet
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// global signal input
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input reset,
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input gclk
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);
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//An EOP or EEP received immediately after an EOP or EEP represents an empty packet
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parameter EOP = 9'b1_0000_0000; // {p,1'b1,8'b0000_0000}
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parameter EEP = 9'b1_0000_0001; // {p,1'b1,8'b0000_0001}
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parameter HEADS_Cargo = 9'b0_xxxx_xxxx; // {p,1'b0,1-byte data }
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// commands
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parameter CMD_WRITE =;
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parameter CMD_REQ_ID =;
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parameter STATENUM = 8;
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parameter RESET = 'b0000_0001;
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parameter IDLE = 'b0000_0010;
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parameter RCV_CMD = 'b0000_0100;
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parameter
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////////////////////////////
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// Register(Control, status)
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//
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reg [7:0] gpio;
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reg [7:0] err;
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reg [7:0] err_source;
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reg [7:0] tim_itv; // timer interval
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reg [9:0] speed [0:IO_PORTNUM]; // to set transmitter speed of each channel individually
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reg [4:0] SWStatus [0:I_PORTNUM]; // switch status
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reg [63:0] LSctrl;
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reg [63:0] CSctrl;
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// Network Management
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reg RouterID; // Router Identity Register
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////////////////////////////
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// Command & Reply
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//
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reg [7:0] cmd [0:13];
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reg [7:0] rpy [0:11];
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always @(posedge gclk)
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endmodule
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endmodule
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`undef reset
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`undef TOOL_NOTSUP_PORT_ARRAY
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