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[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [spwram.vhd] - Diff between revs 2 and 7

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--
 
--
 
--  Synchronous dual-port RAM with separate clocks for read and write ports.
 
--  Synchronous two-port RAM with separate clocks for read and write ports.
 
--  The synthesizer for Xilinx Spartan-3 will infer Block RAM for this entity.
 
--  The synthesizer for Xilinx Spartan-3 will infer Block RAM for this entity.
 
--
 
--
 
 
 
 
 
library ieee;
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_1164.all;

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