| Line 166863... |
Line 166863... |
pclk => after128us[7].CLK
|
pclk => after128us[7].CLK
|
pclk => after128us[8].CLK
|
pclk => after128us[8].CLK
|
pclk => after128us[9].CLK
|
pclk => after128us[9].CLK
|
pclk => after128us[10].CLK
|
pclk => after128us[10].CLK
|
pclk => after128us[11].CLK
|
pclk => after128us[11].CLK
|
|
pclk => get_rx_credit_error_b.CLK
|
|
pclk => get_rx_credit_error_a.CLK
|
|
pclk => get_rx_got_time_code_b.CLK
|
|
pclk => get_rx_got_time_code_a.CLK
|
|
pclk => get_rx_got_nchar_b.CLK
|
|
pclk => get_rx_got_nchar_a.CLK
|
|
pclk => get_rx_got_null_b.CLK
|
|
pclk => get_rx_got_null_a.CLK
|
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pclk => get_rx_error_b.CLK
|
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pclk => get_rx_error_a.CLK
|
|
pclk => get_rx_got_fct_b.CLK
|
|
pclk => get_rx_got_fct_a.CLK
|
pclk => send_fct_tx~reg0.CLK
|
pclk => send_fct_tx~reg0.CLK
|
pclk => send_null_tx~reg0.CLK
|
pclk => send_null_tx~reg0.CLK
|
pclk => enable_tx~reg0.CLK
|
pclk => enable_tx~reg0.CLK
|
pclk => rx_resetn~reg0.CLK
|
pclk => rx_resetn~reg0.CLK
|
pclk => state_fsm~1.DATAIN
|
pclk => state_fsm~1.DATAIN
|
resetn => got_bit_internal.OUTPUTSELECT
|
resetn => got_bit_internal.OUTPUTSELECT
|
|
resetn => get_rx_credit_error_b.ACLR
|
|
resetn => get_rx_credit_error_a.ACLR
|
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resetn => get_rx_got_time_code_b.ACLR
|
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resetn => get_rx_got_time_code_a.ACLR
|
|
resetn => get_rx_got_nchar_b.ACLR
|
|
resetn => get_rx_got_nchar_a.ACLR
|
|
resetn => get_rx_got_null_b.ACLR
|
|
resetn => get_rx_got_null_a.ACLR
|
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resetn => get_rx_error_b.ACLR
|
|
resetn => get_rx_error_a.ACLR
|
|
resetn => get_rx_got_fct_b.ACLR
|
|
resetn => get_rx_got_fct_a.ACLR
|
resetn => send_fct_tx~reg0.ACLR
|
resetn => send_fct_tx~reg0.ACLR
|
resetn => send_null_tx~reg0.ACLR
|
resetn => send_null_tx~reg0.ACLR
|
resetn => enable_tx~reg0.ACLR
|
resetn => enable_tx~reg0.ACLR
|
resetn => rx_resetn~reg0.ACLR
|
resetn => rx_resetn~reg0.ACLR
|
|
resetn => always5.IN1
|
resetn => always2.IN0
|
resetn => always2.IN0
|
resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
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| Line 166886... |
Line 166911... |
resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
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resetn => after64us.OUTPUTSELECT
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resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
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resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
|
resetn => after64us.OUTPUTSELECT
|
resetn => always5.IN1
|
|
resetn => state_fsm~3.DATAIN
|
resetn => state_fsm~3.DATAIN
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auto_start => always0.IN0
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auto_start => always0.IN1
|
auto_start => always3.IN0
|
auto_start => always3.IN0
|
link_start => always0.IN1
|
link_start => always0.IN1
|
link_start => always3.IN1
|
link_start => always3.IN1
|
link_disable => always0.IN1
|
link_disable => always0.IN1
|
link_disable => always0.IN1
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link_disable => always0.IN1
|
rx_error => always0.IN0
|
rx_error => get_rx_error_b.DATAIN
|
rx_error => always0.IN0
|
rx_credit_error => get_rx_credit_error_b.DATAIN
|
rx_error => always0.IN0
|
rx_got_bit => always0.IN1
|
rx_credit_error => always0.IN1
|
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rx_got_bit => always0.IN0
|
|
rx_got_bit => got_bit_internal.DATAB
|
rx_got_bit => got_bit_internal.DATAB
|
rx_got_null => always0.IN1
|
rx_got_null => get_rx_got_null_b.DATAIN
|
rx_got_null => always0.IN1
|
rx_got_nchar => get_rx_got_nchar_b.DATAIN
|
rx_got_nchar => always0.IN1
|
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rx_got_nchar => always0.IN1
|
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rx_got_time_code => always0.IN1
|
rx_got_time_code => always0.IN1
|
rx_got_time_code => always0.IN1
|
rx_got_time_code => get_rx_got_time_code_b.DATAIN
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rx_got_fct => always0.IN1
|
rx_got_fct => get_rx_got_fct_b.DATAIN
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rx_got_fct => next_state_fsm.OUTPUTSELECT
|
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rx_got_fct => next_state_fsm.OUTPUTSELECT
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rx_got_fct => next_state_fsm.OUTPUTSELECT
|
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rx_got_fct => next_state_fsm.OUTPUTSELECT
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rx_got_fct => next_state_fsm.OUTPUTSELECT
|
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rx_got_fct => next_state_fsm.OUTPUTSELECT
|
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rx_resetn <= rx_resetn~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_resetn <= rx_resetn~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx <= enable_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx <= enable_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
send_null_tx <= send_null_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
send_null_tx <= send_null_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
send_fct_tx <= send_fct_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
send_fct_tx <= send_fct_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
fsm_state[0] <= fsm_state[0].DB_MAX_OUTPUT_PORT_TYPE
|
fsm_state[0] <= fsm_state[0].DB_MAX_OUTPUT_PORT_TYPE
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| Line 166926... |
Line 166940... |
fsm_state[4] <= fsm_state[4].DB_MAX_OUTPUT_PORT_TYPE
|
fsm_state[4] <= fsm_state[4].DB_MAX_OUTPUT_PORT_TYPE
|
fsm_state[5] <=
|
fsm_state[5] <=
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX
|
rx_din => always0.IN0
|
rx_din => rx_din.IN3
|
rx_din => always3.IN0
|
rx_sin => comb.IN0
|
rx_din => control_bit_found.DATAIN
|
rx_sin => always1.IN0
|
rx_din => bit_c_0.DATAIN
|
rx_resetn => rx_resetn.IN8
|
rx_din => bit_c_1.DATAIN
|
rx_error <= rx_control_data_rdy:control_data_rdy.rx_error
|
rx_din => bit_d_0.DATAIN
|
rx_got_bit <= always1.DB_MAX_OUTPUT_PORT_TYPE
|
rx_din => bit_d_1.DATAIN
|
rx_got_null <= rx_buffer_fsm:buffer_fsm.rx_got_null
|
rx_sin => always0.IN1
|
rx_got_nchar <= rx_buffer_fsm:buffer_fsm.rx_got_nchar
|
rx_sin => always3.IN1
|
rx_got_time_code <= rx_buffer_fsm:buffer_fsm.rx_got_time_code
|
rx_resetn => last_was_timec.ACLR
|
rx_got_fct <= rx_data_receive:rx_dtarcv.rx_got_fct
|
rx_resetn => last_was_data.ACLR
|
rx_got_fct_fsm <= rx_control_data_rdy:control_data_rdy.rx_got_fct_fsm
|
rx_resetn => last_was_control.ACLR
|
rx_data_flag[0] <= rx_data_receive:rx_dtarcv.rx_data_flag
|
rx_resetn => last_is_timec.ACLR
|
rx_data_flag[1] <= rx_data_receive:rx_dtarcv.rx_data_flag
|
rx_resetn => last_is_data.ACLR
|
rx_data_flag[2] <= rx_data_receive:rx_dtarcv.rx_data_flag
|
rx_resetn => last_is_control.ACLR
|
rx_data_flag[3] <= rx_data_receive:rx_dtarcv.rx_data_flag
|
|
rx_data_flag[4] <= rx_data_receive:rx_dtarcv.rx_data_flag
|
|
rx_data_flag[5] <= rx_data_receive:rx_dtarcv.rx_data_flag
|
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rx_data_flag[6] <= rx_data_receive:rx_dtarcv.rx_data_flag
|
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rx_data_flag[7] <= rx_data_receive:rx_dtarcv.rx_data_flag
|
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rx_data_flag[8] <= rx_data_receive:rx_dtarcv.rx_data_flag
|
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rx_buffer_write <= rx_data_buffer_data_w:buffer_data_flag.rx_buffer_write
|
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rx_time_out[0] <= rx_time_out[0].DB_MAX_OUTPUT_PORT_TYPE
|
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rx_time_out[1] <= rx_time_out[1].DB_MAX_OUTPUT_PORT_TYPE
|
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rx_time_out[2] <= rx_time_out[2].DB_MAX_OUTPUT_PORT_TYPE
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rx_time_out[3] <= rx_time_out[3].DB_MAX_OUTPUT_PORT_TYPE
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rx_time_out[4] <= rx_time_out[4].DB_MAX_OUTPUT_PORT_TYPE
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rx_time_out[5] <= rx_time_out[5].DB_MAX_OUTPUT_PORT_TYPE
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rx_time_out[6] <= rx_time_out[6].DB_MAX_OUTPUT_PORT_TYPE
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rx_time_out[7] <= rx_time_out[7].DB_MAX_OUTPUT_PORT_TYPE
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rx_tick_out <= rx_data_buffer_data_w:buffer_data_flag.rx_tick_out
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|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_buffer_fsm:buffer_fsm
|
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posedge_clk => rx_got_time_code~reg0.CLK
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posedge_clk => rx_got_nchar~reg0.CLK
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posedge_clk => rx_got_null~reg0.CLK
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rx_resetn => rx_got_time_code~reg0.ACLR
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rx_resetn => rx_got_nchar~reg0.ACLR
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rx_resetn => rx_got_null~reg0.ACLR
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last_is_data => rx_got_null.OUTPUTSELECT
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last_is_data => rx_got_time_code.OUTPUTSELECT
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last_is_data => rx_got_nchar~reg0.DATAIN
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last_is_timec => rx_got_null.OUTPUTSELECT
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last_is_timec => rx_got_time_code.DATAA
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last_is_control => rx_got_null.DATAA
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rx_got_null <= rx_got_null~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_got_nchar <= rx_got_nchar~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_got_time_code <= rx_got_time_code~reg0.DB_MAX_OUTPUT_PORT_TYPE
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|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_buffer_data_w:buffer_data_flag
|
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negedge_clk => rx_tick_out~reg0.CLK
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negedge_clk => rx_buffer_write~reg0.CLK
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rx_resetn => rx_tick_out~reg0.ACLR
|
rx_resetn => rx_tick_out~reg0.ACLR
|
rx_resetn => timecode[0].ACLR
|
rx_resetn => rx_buffer_write~reg0.ACLR
|
rx_resetn => timecode[1].ACLR
|
state_data_process[0] => Equal0.IN0
|
rx_resetn => timecode[2].ACLR
|
state_data_process[1] => Equal0.IN1
|
rx_resetn => timecode[3].ACLR
|
control[0] => Equal1.IN2
|
rx_resetn => timecode[4].ACLR
|
control[0] => Equal2.IN1
|
rx_resetn => timecode[5].ACLR
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control[1] => Equal1.IN1
|
rx_resetn => timecode[6].ACLR
|
control[1] => Equal2.IN2
|
rx_resetn => timecode[7].ACLR
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control[2] => Equal1.IN0
|
rx_resetn => rx_data_take.ACLR
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control[2] => Equal2.IN0
|
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last_is_timec => rx_buffer_write.OUTPUTSELECT
|
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last_is_timec => rx_tick_out.DATAB
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last_is_data => rx_buffer_write.OUTPUTSELECT
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last_is_control => rx_buffer_write.OUTPUTSELECT
|
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rx_buffer_write <= rx_buffer_write~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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rx_tick_out <= rx_tick_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy
|
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posedge_clk => rx_error~reg0.CLK
|
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posedge_clk => ready_data_p_r~reg0.CLK
|
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posedge_clk => ready_control_p_r~reg0.CLK
|
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posedge_clk => rx_got_fct_fsm~reg0.CLK
|
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rx_resetn => rx_error~reg0.ACLR
|
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rx_resetn => ready_data_p_r~reg0.ACLR
|
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rx_resetn => ready_control_p_r~reg0.ACLR
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rx_resetn => rx_got_fct_fsm~reg0.ACLR
|
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rx_error_c => rx_error.IN0
|
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rx_error_d => rx_error.IN1
|
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control[0] => Equal3.IN2
|
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control[1] => Equal3.IN1
|
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control[2] => Equal3.IN0
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control_l_r[0] => Equal2.IN2
|
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control_l_r[1] => Equal2.IN1
|
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control_l_r[2] => Equal2.IN0
|
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is_control => always0.IN1
|
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counter_neg[0] => Equal0.IN5
|
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counter_neg[0] => Equal1.IN5
|
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counter_neg[1] => Equal0.IN4
|
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counter_neg[1] => Equal1.IN4
|
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counter_neg[2] => Equal0.IN0
|
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counter_neg[2] => Equal1.IN3
|
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counter_neg[3] => Equal0.IN3
|
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counter_neg[3] => Equal1.IN2
|
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counter_neg[4] => Equal0.IN2
|
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counter_neg[4] => Equal1.IN1
|
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counter_neg[5] => Equal0.IN1
|
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counter_neg[5] => Equal1.IN0
|
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last_is_control => always0.IN1
|
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rx_error <= rx_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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ready_control_p_r <= ready_control_p_r~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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ready_data_p_r <= ready_data_p_r~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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rx_got_fct_fsm <= rx_got_fct_fsm~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control
|
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posedge_clk => parity_rec_c_gen~reg0.CLK
|
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posedge_clk => parity_rec_c~reg0.CLK
|
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posedge_clk => control_l_r[0]~reg0.CLK
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posedge_clk => control_l_r[1]~reg0.CLK
|
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posedge_clk => control_l_r[2]~reg0.CLK
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posedge_clk => control_p_r[0]~reg0.CLK
|
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posedge_clk => control_p_r[1]~reg0.CLK
|
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posedge_clk => control_p_r[2]~reg0.CLK
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posedge_clk => dta_timec_p[0]~reg0.CLK
|
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posedge_clk => dta_timec_p[1]~reg0.CLK
|
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posedge_clk => dta_timec_p[2]~reg0.CLK
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posedge_clk => dta_timec_p[3]~reg0.CLK
|
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posedge_clk => dta_timec_p[4]~reg0.CLK
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posedge_clk => dta_timec_p[5]~reg0.CLK
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posedge_clk => dta_timec_p[6]~reg0.CLK
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posedge_clk => dta_timec_p[7]~reg0.CLK
|
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posedge_clk => dta_timec_p[8]~reg0.CLK
|
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posedge_clk => parity_rec_d_gen~reg0.CLK
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posedge_clk => parity_rec_d~reg0.CLK
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rx_resetn => dta_timec_p[0]~reg0.ACLR
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rx_resetn => dta_timec_p[1]~reg0.ACLR
|
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rx_resetn => dta_timec_p[2]~reg0.ACLR
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rx_resetn => dta_timec_p[3]~reg0.ACLR
|
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rx_resetn => dta_timec_p[4]~reg0.ACLR
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rx_resetn => dta_timec_p[5]~reg0.ACLR
|
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rx_resetn => dta_timec_p[6]~reg0.ACLR
|
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rx_resetn => dta_timec_p[7]~reg0.ACLR
|
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rx_resetn => dta_timec_p[8]~reg0.ACLR
|
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rx_resetn => parity_rec_d_gen~reg0.ACLR
|
|
rx_resetn => parity_rec_d~reg0.ACLR
|
|
rx_resetn => parity_rec_c_gen~reg0.ACLR
|
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rx_resetn => parity_rec_c~reg0.ACLR
|
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rx_resetn => control_l_r[0]~reg0.ACLR
|
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rx_resetn => control_l_r[1]~reg0.ACLR
|
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rx_resetn => control_l_r[2]~reg0.ACLR
|
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rx_resetn => control_p_r[0]~reg0.ACLR
|
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rx_resetn => control_p_r[1]~reg0.ACLR
|
|
rx_resetn => control_p_r[2]~reg0.ACLR
|
|
bit_c_3 => parity_rec_c~reg0.DATAIN
|
|
bit_c_2 => parity_rec_c_gen.IN1
|
|
bit_c_2 => parity_rec_c_gen.IN1
|
|
bit_c_2 => control_p_r[2]~reg0.DATAIN
|
|
bit_c_1 => control_p_r[1]~reg0.DATAIN
|
|
bit_c_0 => control_p_r[0]~reg0.DATAIN
|
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bit_d_9 => parity_rec_d~reg0.DATAIN
|
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bit_d_8 => parity_rec_d_gen.IN1
|
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bit_d_8 => parity_rec_d_gen.IN1
|
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bit_d_8 => dta_timec_p[8]~reg0.DATAIN
|
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bit_d_0 => dta_timec_p[7]~reg0.DATAIN
|
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bit_d_1 => dta_timec_p[6]~reg0.DATAIN
|
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bit_d_2 => dta_timec_p[5]~reg0.DATAIN
|
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bit_d_3 => dta_timec_p[4]~reg0.DATAIN
|
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bit_d_4 => dta_timec_p[3]~reg0.DATAIN
|
|
bit_d_5 => dta_timec_p[2]~reg0.DATAIN
|
|
bit_d_6 => dta_timec_p[1]~reg0.DATAIN
|
|
bit_d_7 => dta_timec_p[0]~reg0.DATAIN
|
|
last_is_control => parity_rec_d_gen.OUTPUTSELECT
|
|
last_is_control => parity_rec_c_gen.OUTPUTSELECT
|
|
last_is_data => parity_rec_d_gen.OUTPUTSELECT
|
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last_is_data => parity_rec_c_gen.OUTPUTSELECT
|
|
is_control => always0.IN1
|
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is_control => always1.IN1
|
|
counter_neg[0] => Equal0.IN5
|
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counter_neg[0] => Equal1.IN5
|
|
counter_neg[1] => Equal0.IN4
|
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counter_neg[1] => Equal1.IN4
|
|
counter_neg[2] => Equal0.IN3
|
|
counter_neg[2] => Equal1.IN0
|
|
counter_neg[3] => Equal0.IN2
|
|
counter_neg[3] => Equal1.IN3
|
|
counter_neg[4] => Equal0.IN1
|
|
counter_neg[4] => Equal1.IN2
|
|
counter_neg[5] => Equal0.IN0
|
|
counter_neg[5] => Equal1.IN1
|
|
dta_timec_p[0] <= dta_timec_p[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
dta_timec_p[1] <= dta_timec_p[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
dta_timec_p[2] <= dta_timec_p[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
dta_timec_p[3] <= dta_timec_p[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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dta_timec_p[4] <= dta_timec_p[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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dta_timec_p[5] <= dta_timec_p[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
dta_timec_p[6] <= dta_timec_p[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
dta_timec_p[7] <= dta_timec_p[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
dta_timec_p[8] <= dta_timec_p[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
parity_rec_d <= parity_rec_d~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
parity_rec_d_gen <= parity_rec_d_gen~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
control_p_r[0] <= control_p_r[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
control_p_r[1] <= control_p_r[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
control_p_r[2] <= control_p_r[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
control_l_r[0] <= control_l_r[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
control_l_r[1] <= control_l_r[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
control_l_r[2] <= control_l_r[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
parity_rec_c <= parity_rec_c~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
parity_rec_c_gen <= parity_rec_c_gen~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d
|
|
negedge_clk => bit_d_8~reg0.CLK
|
|
negedge_clk => bit_d_6~reg0.CLK
|
|
negedge_clk => bit_d_4~reg0.CLK
|
|
negedge_clk => bit_d_2~reg0.CLK
|
|
negedge_clk => bit_d_0~reg0.CLK
|
|
posedge_clk => bit_d_9~reg0.CLK
|
|
posedge_clk => bit_d_7~reg0.CLK
|
|
posedge_clk => bit_d_5~reg0.CLK
|
|
posedge_clk => bit_d_3~reg0.CLK
|
|
posedge_clk => bit_d_1~reg0.CLK
|
|
rx_resetn => bit_d_8~reg0.ACLR
|
|
rx_resetn => bit_d_6~reg0.ACLR
|
|
rx_resetn => bit_d_4~reg0.ACLR
|
|
rx_resetn => bit_d_2~reg0.ACLR
|
|
rx_resetn => bit_d_0~reg0.ACLR
|
|
rx_resetn => bit_d_9~reg0.ACLR
|
|
rx_resetn => bit_d_7~reg0.ACLR
|
|
rx_resetn => bit_d_5~reg0.ACLR
|
|
rx_resetn => bit_d_3~reg0.ACLR
|
|
rx_resetn => bit_d_1~reg0.ACLR
|
|
rx_din => bit_d_0~reg0.DATAIN
|
|
rx_din => bit_d_1~reg0.DATAIN
|
|
bit_d_0 <= bit_d_0~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_1 <= bit_d_1~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_2 <= bit_d_2~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_3 <= bit_d_3~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_4 <= bit_d_4~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_5 <= bit_d_5~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_6 <= bit_d_6~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_7 <= bit_d_7~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_8 <= bit_d_8~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_9 <= bit_d_9~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c
|
|
negedge_clk => bit_c_2~reg0.CLK
|
|
negedge_clk => bit_c_0~reg0.CLK
|
|
posedge_clk => bit_c_3~reg0.CLK
|
|
posedge_clk => bit_c_1~reg0.CLK
|
|
rx_resetn => bit_c_2~reg0.ACLR
|
|
rx_resetn => bit_c_0~reg0.ACLR
|
|
rx_resetn => bit_c_3~reg0.ACLR
|
|
rx_resetn => bit_c_1~reg0.ACLR
|
|
rx_din => bit_c_0~reg0.DATAIN
|
|
rx_din => bit_c_1~reg0.DATAIN
|
|
bit_c_0 <= bit_c_0~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_c_1 <= bit_c_1~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_c_2 <= bit_c_2~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_c_3 <= bit_c_3~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg
|
|
negedge_clk => counter_neg[0]~reg0.CLK
|
|
negedge_clk => counter_neg[1]~reg0.CLK
|
|
negedge_clk => counter_neg[2]~reg0.CLK
|
|
negedge_clk => counter_neg[3]~reg0.CLK
|
|
negedge_clk => counter_neg[4]~reg0.CLK
|
|
negedge_clk => counter_neg[5]~reg0.CLK
|
|
negedge_clk => control_bit_found.CLK
|
|
negedge_clk => is_control~reg0.CLK
|
|
rx_resetn => counter_neg[0]~reg0.PRESET
|
|
rx_resetn => counter_neg[1]~reg0.ACLR
|
|
rx_resetn => counter_neg[2]~reg0.ACLR
|
|
rx_resetn => counter_neg[3]~reg0.ACLR
|
|
rx_resetn => counter_neg[4]~reg0.ACLR
|
|
rx_resetn => counter_neg[5]~reg0.ACLR
|
|
rx_resetn => control_bit_found.ACLR
|
|
rx_resetn => is_control~reg0.ACLR
|
|
rx_din => control_bit_found.DATAIN
|
|
is_control <= is_control~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter_neg[0] <= counter_neg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter_neg[1] <= counter_neg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter_neg[2] <= counter_neg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter_neg[3] <= counter_neg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter_neg[4] <= counter_neg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter_neg[5] <= counter_neg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv
|
|
posedge_clk => rx_got_fct~reg0.CLK
|
|
posedge_clk => rx_error_d~reg0.CLK
|
|
posedge_clk => rx_error_c~reg0.CLK
|
|
posedge_clk => state_data_process[0]~reg0.CLK
|
|
posedge_clk => state_data_process[1]~reg0.CLK
|
|
posedge_clk => timecode[0]~reg0.CLK
|
|
posedge_clk => timecode[1]~reg0.CLK
|
|
posedge_clk => timecode[2]~reg0.CLK
|
|
posedge_clk => timecode[3]~reg0.CLK
|
|
posedge_clk => timecode[4]~reg0.CLK
|
|
posedge_clk => timecode[5]~reg0.CLK
|
|
posedge_clk => timecode[6]~reg0.CLK
|
|
posedge_clk => timecode[7]~reg0.CLK
|
|
posedge_clk => rx_data_flag[0]~reg0.CLK
|
|
posedge_clk => rx_data_flag[1]~reg0.CLK
|
|
posedge_clk => rx_data_flag[2]~reg0.CLK
|
|
posedge_clk => rx_data_flag[3]~reg0.CLK
|
|
posedge_clk => rx_data_flag[4]~reg0.CLK
|
|
posedge_clk => rx_data_flag[5]~reg0.CLK
|
|
posedge_clk => rx_data_flag[6]~reg0.CLK
|
|
posedge_clk => rx_data_flag[7]~reg0.CLK
|
|
posedge_clk => rx_data_flag[8]~reg0.CLK
|
|
posedge_clk => last_is_timec~reg0.CLK
|
|
posedge_clk => last_is_data~reg0.CLK
|
|
posedge_clk => last_is_control~reg0.CLK
|
|
rx_resetn => rx_got_fct~reg0.ACLR
|
|
rx_resetn => rx_error_d~reg0.ACLR
|
|
rx_resetn => rx_error_c~reg0.ACLR
|
|
rx_resetn => state_data_process[0]~reg0.ACLR
|
|
rx_resetn => state_data_process[1]~reg0.ACLR
|
|
rx_resetn => timecode[0]~reg0.ACLR
|
|
rx_resetn => timecode[1]~reg0.ACLR
|
|
rx_resetn => timecode[2]~reg0.ACLR
|
|
rx_resetn => timecode[3]~reg0.ACLR
|
|
rx_resetn => timecode[4]~reg0.ACLR
|
|
rx_resetn => timecode[5]~reg0.ACLR
|
|
rx_resetn => timecode[6]~reg0.ACLR
|
|
rx_resetn => timecode[7]~reg0.ACLR
|
rx_resetn => rx_data_flag[0]~reg0.ACLR
|
rx_resetn => rx_data_flag[0]~reg0.ACLR
|
rx_resetn => rx_data_flag[1]~reg0.ACLR
|
rx_resetn => rx_data_flag[1]~reg0.ACLR
|
rx_resetn => rx_data_flag[2]~reg0.ACLR
|
rx_resetn => rx_data_flag[2]~reg0.ACLR
|
rx_resetn => rx_data_flag[3]~reg0.ACLR
|
rx_resetn => rx_data_flag[3]~reg0.ACLR
|
rx_resetn => rx_data_flag[4]~reg0.ACLR
|
rx_resetn => rx_data_flag[4]~reg0.ACLR
|
rx_resetn => rx_data_flag[5]~reg0.ACLR
|
rx_resetn => rx_data_flag[5]~reg0.ACLR
|
rx_resetn => rx_data_flag[6]~reg0.ACLR
|
rx_resetn => rx_data_flag[6]~reg0.ACLR
|
rx_resetn => rx_data_flag[7]~reg0.ACLR
|
rx_resetn => rx_data_flag[7]~reg0.ACLR
|
rx_resetn => rx_data_flag[8]~reg0.ACLR
|
rx_resetn => rx_data_flag[8]~reg0.ACLR
|
rx_resetn => data_l_r[1].ACLR
|
rx_resetn => last_is_timec~reg0.ACLR
|
rx_resetn => data_l_r[2].ACLR
|
rx_resetn => last_is_data~reg0.ACLR
|
rx_resetn => data_l_r[3].ACLR
|
rx_resetn => last_is_control~reg0.ACLR
|
rx_resetn => data_l_r[4].ACLR
|
ready_control_p_r => always0.IN0
|
rx_resetn => data_l_r[5].ACLR
|
ready_control_p_r => rx_got_fct.OUTPUTSELECT
|
rx_resetn => data_l_r[6].ACLR
|
ready_control_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => data_l_r[7].ACLR
|
ready_control_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => data[0].ACLR
|
ready_control_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => data[1].ACLR
|
ready_control_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => data[2].ACLR
|
ready_control_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => data[3].ACLR
|
ready_control_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => data[4].ACLR
|
ready_control_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => data[5].ACLR
|
ready_control_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => data[6].ACLR
|
ready_control_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => data[7].ACLR
|
ready_control_p_r => last_is_control.OUTPUTSELECT
|
rx_resetn => data[8].ACLR
|
ready_control_p_r => last_is_data.OUTPUTSELECT
|
rx_resetn => data[9].ACLR
|
ready_control_p_r => last_is_timec.OUTPUTSELECT
|
rx_resetn => control[0].ACLR
|
ready_control_p_r => timecode.OUTPUTSELECT
|
rx_resetn => control[1].ACLR
|
ready_control_p_r => timecode.OUTPUTSELECT
|
rx_resetn => control[2].ACLR
|
ready_control_p_r => timecode.OUTPUTSELECT
|
rx_resetn => control[3].ACLR
|
ready_control_p_r => timecode.OUTPUTSELECT
|
rx_resetn => control_l_r[0].ACLR
|
ready_control_p_r => timecode.OUTPUTSELECT
|
rx_resetn => control_l_r[1].ACLR
|
ready_control_p_r => timecode.OUTPUTSELECT
|
rx_resetn => control_l_r[2].ACLR
|
ready_control_p_r => timecode.OUTPUTSELECT
|
rx_resetn => rx_got_time_code~reg0.ACLR
|
ready_control_p_r => timecode.OUTPUTSELECT
|
rx_resetn => rx_got_nchar~reg0.ACLR
|
ready_control_p_r => rx_error_c.OUTPUTSELECT
|
rx_resetn => rx_got_null~reg0.ACLR
|
ready_control_p_r => rx_got_fct.OUTPUTSELECT
|
rx_resetn => rx_error~reg0.ACLR
|
ready_control_p_r => rx_error_d.OUTPUTSELECT
|
rx_resetn => rx_got_fct~reg0.ACLR
|
ready_data_p_r => always0.IN1
|
rx_resetn => ready_data_p_r.ACLR
|
ready_data_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => ready_control_p_r.ACLR
|
ready_data_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => rx_data_take_0.ACLR
|
ready_data_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => rx_buffer_write~reg0.ACLR
|
ready_data_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => rx_got_fct_fsm~reg0.ACLR
|
ready_data_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => bit_d_9.ACLR
|
ready_data_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => bit_d_7.ACLR
|
ready_data_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => bit_d_5.ACLR
|
ready_data_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => bit_d_3.ACLR
|
ready_data_p_r => rx_data_flag.OUTPUTSELECT
|
rx_resetn => bit_d_1.ACLR
|
ready_data_p_r => last_is_control.OUTPUTSELECT
|
rx_resetn => bit_d_8.ACLR
|
ready_data_p_r => last_is_data.OUTPUTSELECT
|
rx_resetn => bit_d_6.ACLR
|
ready_data_p_r => last_is_timec.OUTPUTSELECT
|
rx_resetn => bit_d_4.ACLR
|
ready_data_p_r => timecode.OUTPUTSELECT
|
rx_resetn => bit_d_2.ACLR
|
ready_data_p_r => timecode.OUTPUTSELECT
|
rx_resetn => bit_d_0.ACLR
|
ready_data_p_r => timecode.OUTPUTSELECT
|
rx_resetn => bit_c_3.ACLR
|
ready_data_p_r => timecode.OUTPUTSELECT
|
rx_resetn => bit_c_1.ACLR
|
ready_data_p_r => timecode.OUTPUTSELECT
|
rx_resetn => bit_c_2.ACLR
|
ready_data_p_r => timecode.OUTPUTSELECT
|
rx_resetn => bit_c_0.ACLR
|
ready_data_p_r => timecode.OUTPUTSELECT
|
rx_resetn => control_r[0].ACLR
|
ready_data_p_r => timecode.OUTPUTSELECT
|
rx_resetn => control_r[1].ACLR
|
ready_data_p_r => rx_error_d.OUTPUTSELECT
|
rx_resetn => control_r[2].ACLR
|
ready_control => always0.IN0
|
rx_resetn => control_r[3].ACLR
|
ready_data => always0.IN1
|
rx_resetn => control_p_r[0].ACLR
|
parity_rec_c => always1.IN0
|
rx_resetn => control_p_r[1].ACLR
|
parity_rec_d => always1.IN0
|
rx_resetn => control_p_r[2].ACLR
|
parity_rec_c_gen => always1.IN1
|
rx_resetn => control_p_r[3].ACLR
|
parity_rec_d_gen => always1.IN1
|
rx_resetn => dta_timec[0].ACLR
|
control_p_r[0] => Equal3.IN2
|
rx_resetn => dta_timec[1].ACLR
|
control_p_r[0] => Equal4.IN2
|
rx_resetn => dta_timec[2].ACLR
|
control_p_r[0] => Equal5.IN1
|
rx_resetn => dta_timec[3].ACLR
|
control_p_r[0] => Equal6.IN2
|
rx_resetn => dta_timec[4].ACLR
|
control_p_r[1] => Equal3.IN1
|
rx_resetn => dta_timec[5].ACLR
|
control_p_r[1] => Equal4.IN1
|
rx_resetn => dta_timec[6].ACLR
|
control_p_r[1] => Equal5.IN2
|
rx_resetn => dta_timec[7].ACLR
|
control_p_r[1] => Equal6.IN1
|
rx_resetn => dta_timec[8].ACLR
|
control_p_r[2] => Equal3.IN0
|
rx_resetn => dta_timec[9].ACLR
|
control_p_r[2] => Equal4.IN0
|
rx_resetn => dta_timec_p[0].ACLR
|
control_p_r[2] => Equal5.IN0
|
rx_resetn => dta_timec_p[1].ACLR
|
control_p_r[2] => Equal6.IN0
|
rx_resetn => dta_timec_p[2].ACLR
|
control_l_r[0] => Equal2.IN2
|
rx_resetn => dta_timec_p[3].ACLR
|
control_l_r[1] => Equal2.IN1
|
rx_resetn => dta_timec_p[4].ACLR
|
control_l_r[2] => Equal2.IN0
|
rx_resetn => dta_timec_p[5].ACLR
|
dta_timec_p[0] => timecode.DATAB
|
rx_resetn => dta_timec_p[6].ACLR
|
dta_timec_p[0] => rx_data_flag.DATAB
|
rx_resetn => dta_timec_p[7].ACLR
|
dta_timec_p[1] => timecode.DATAB
|
rx_resetn => dta_timec_p[8].ACLR
|
dta_timec_p[1] => rx_data_flag.DATAB
|
rx_resetn => dta_timec_p[9].ACLR
|
dta_timec_p[2] => timecode.DATAB
|
rx_resetn => counter_neg[0].PRESET
|
dta_timec_p[2] => rx_data_flag.DATAB
|
rx_resetn => counter_neg[1].ACLR
|
dta_timec_p[3] => timecode.DATAB
|
rx_resetn => counter_neg[2].ACLR
|
dta_timec_p[3] => rx_data_flag.DATAB
|
rx_resetn => counter_neg[3].ACLR
|
dta_timec_p[4] => timecode.DATAB
|
rx_resetn => counter_neg[4].ACLR
|
dta_timec_p[4] => rx_data_flag.DATAB
|
rx_resetn => counter_neg[5].ACLR
|
dta_timec_p[5] => timecode.DATAB
|
rx_resetn => control_bit_found.ACLR
|
dta_timec_p[5] => rx_data_flag.DATAB
|
rx_resetn => is_control.ACLR
|
dta_timec_p[6] => timecode.DATAB
|
rx_error <= rx_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
dta_timec_p[6] => rx_data_flag.DATAB
|
rx_got_bit <= always0.DB_MAX_OUTPUT_PORT_TYPE
|
dta_timec_p[7] => timecode.DATAB
|
rx_got_null <= rx_got_null~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
dta_timec_p[7] => rx_data_flag.DATAB
|
rx_got_nchar <= rx_got_nchar~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
dta_timec_p[8] => rx_data_flag.DATAB
|
rx_got_time_code <= rx_got_time_code~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
state_data_process[0] <= state_data_process[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
state_data_process[1] <= state_data_process[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
last_is_control <= last_is_control~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
last_is_data <= last_is_data~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
last_is_timec <= last_is_timec~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rx_error_c <= rx_error_c~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rx_error_d <= rx_error_d~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_got_fct <= rx_got_fct~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_got_fct <= rx_got_fct~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_got_fct_fsm <= rx_got_fct_fsm~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rx_data_flag[0] <= rx_data_flag[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[0] <= rx_data_flag[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[1] <= rx_data_flag[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[1] <= rx_data_flag[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[2] <= rx_data_flag[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[2] <= rx_data_flag[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[3] <= rx_data_flag[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[3] <= rx_data_flag[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[4] <= rx_data_flag[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[4] <= rx_data_flag[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[5] <= rx_data_flag[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[5] <= rx_data_flag[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[6] <= rx_data_flag[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[6] <= rx_data_flag[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[7] <= rx_data_flag[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[7] <= rx_data_flag[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[8] <= rx_data_flag[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_data_flag[8] <= rx_data_flag[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_buffer_write <= rx_buffer_write~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
timecode[0] <= timecode[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_time_out[0] <= timecode[0].DB_MAX_OUTPUT_PORT_TYPE
|
timecode[1] <= timecode[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_time_out[1] <= timecode[1].DB_MAX_OUTPUT_PORT_TYPE
|
timecode[2] <= timecode[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_time_out[2] <= timecode[2].DB_MAX_OUTPUT_PORT_TYPE
|
timecode[3] <= timecode[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_time_out[3] <= timecode[3].DB_MAX_OUTPUT_PORT_TYPE
|
timecode[4] <= timecode[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_time_out[4] <= timecode[4].DB_MAX_OUTPUT_PORT_TYPE
|
timecode[5] <= timecode[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_time_out[5] <= timecode[5].DB_MAX_OUTPUT_PORT_TYPE
|
timecode[6] <= timecode[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_time_out[6] <= timecode[6].DB_MAX_OUTPUT_PORT_TYPE
|
timecode[7] <= timecode[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rx_time_out[7] <= timecode[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
rx_tick_out <= rx_tick_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX
|
pclk_tx => last_tx_sout.CLK
|
pclk_tx => pclk_tx.IN2
|
pclk_tx => last_tx_dout.CLK
|
data_tx_i[0] => data_tx_i[0].IN1
|
pclk_tx => block_sum_fct_send.CLK
|
data_tx_i[1] => data_tx_i[1].IN1
|
pclk_tx => block_sum.CLK
|
data_tx_i[2] => data_tx_i[2].IN1
|
|
data_tx_i[3] => data_tx_i[3].IN1
|
|
data_tx_i[4] => data_tx_i[4].IN1
|
|
data_tx_i[5] => data_tx_i[5].IN1
|
|
data_tx_i[6] => data_tx_i[6].IN1
|
|
data_tx_i[7] => data_tx_i[7].IN1
|
|
data_tx_i[8] => data_tx_i[8].IN1
|
|
txwrite_tx => txwrite_tx.IN1
|
|
timecode_tx_i[0] => timecode_tx_i[0].IN1
|
|
timecode_tx_i[1] => timecode_tx_i[1].IN1
|
|
timecode_tx_i[2] => timecode_tx_i[2].IN1
|
|
timecode_tx_i[3] => timecode_tx_i[3].IN1
|
|
timecode_tx_i[4] => timecode_tx_i[4].IN1
|
|
timecode_tx_i[5] => timecode_tx_i[5].IN1
|
|
timecode_tx_i[6] => timecode_tx_i[6].IN1
|
|
timecode_tx_i[7] => timecode_tx_i[7].IN1
|
|
tickin_tx => tickin_tx.IN1
|
|
enable_tx => enable_tx.IN2
|
|
send_null_tx => send_null_tx.IN1
|
|
send_fct_tx => send_fct_tx.IN1
|
|
gotfct_tx => gotfct_tx.IN1
|
|
send_fct_now => send_fct_now.IN1
|
|
ready_tx_data <= tx_fsm_m:tx_fsm.ready_tx_data
|
|
ready_tx_timecode <= tx_fsm_m:tx_fsm.ready_tx_timecode
|
|
tx_dout_e <= tx_fsm_m:tx_fsm.tx_dout_e
|
|
tx_sout_e <= tx_fsm_m:tx_fsm.tx_sout_e
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm
|
|
pclk_tx => pclk_tx.IN2
|
|
enable_tx => enable_tx.IN2
|
|
send_null_tx => always0.IN0
|
|
send_null_tx => last_tx_dout.OUTPUTSELECT
|
|
send_null_tx => last_tx_sout.OUTPUTSELECT
|
|
send_null_tx => tx_dout_e.OUTPUTSELECT
|
|
send_null_tx => tx_sout_e.OUTPUTSELECT
|
|
send_null_tx => global_counter_transfer.OUTPUTSELECT
|
|
send_null_tx => global_counter_transfer.OUTPUTSELECT
|
|
send_null_tx => global_counter_transfer.OUTPUTSELECT
|
|
send_null_tx => global_counter_transfer.OUTPUTSELECT
|
|
send_null_tx => Selector1.IN5
|
|
send_null_tx => Selector0.IN1
|
|
send_fct_tx => always0.IN1
|
|
send_fct_tx => always0.IN1
|
|
tx_data_in[0] => ShiftRight1.IN10
|
|
tx_data_in[0] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in[0] => Equal0.IN1
|
|
tx_data_in[0] => Equal1.IN1
|
|
tx_data_in[1] => ShiftRight1.IN9
|
|
tx_data_in[1] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in[1] => Equal0.IN0
|
|
tx_data_in[1] => Equal1.IN0
|
|
tx_data_in[2] => ShiftRight1.IN8
|
|
tx_data_in[2] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in[3] => ShiftRight1.IN7
|
|
tx_data_in[3] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in[4] => ShiftRight1.IN6
|
|
tx_data_in[4] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in[5] => ShiftRight1.IN5
|
|
tx_data_in[5] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in[6] => ShiftRight1.IN4
|
|
tx_data_in[6] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in[7] => ShiftRight1.IN3
|
|
tx_data_in[7] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in[8] => result_shift.IN1
|
|
tx_data_in[8] => result_shift.IN1
|
|
tx_data_in[8] => counter_aux.IN0
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in[8] => ready_tx_data.OUTPUTSELECT
|
|
tx_data_in[8] => char_sent.OUTPUTSELECT
|
|
tx_data_in[8] => counter_aux.IN0
|
|
tx_data_in[8] => result_shift.IN0
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in[8] => always1.IN0
|
|
tx_data_in_0[0] => ShiftRight2.IN10
|
|
tx_data_in_0[0] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in_0[0] => Equal2.IN1
|
|
tx_data_in_0[0] => Equal3.IN1
|
|
tx_data_in_0[1] => ShiftRight2.IN9
|
|
tx_data_in_0[1] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in_0[1] => Equal2.IN0
|
|
tx_data_in_0[1] => Equal3.IN0
|
|
tx_data_in_0[2] => ShiftRight2.IN8
|
|
tx_data_in_0[2] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in_0[3] => ShiftRight2.IN7
|
|
tx_data_in_0[3] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in_0[4] => ShiftRight2.IN6
|
|
tx_data_in_0[4] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in_0[5] => ShiftRight2.IN5
|
|
tx_data_in_0[5] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in_0[6] => ShiftRight2.IN4
|
|
tx_data_in_0[6] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in_0[7] => ShiftRight2.IN3
|
|
tx_data_in_0[7] => txdata_flagctrl_tx_last.DATAB
|
|
tx_data_in_0[8] => result_shift.IN1
|
|
tx_data_in_0[8] => result_shift.IN1
|
|
tx_data_in_0[8] => counter_aux.IN1
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
|
tx_data_in_0[8] => ready_tx_data.OUTPUTSELECT
|
|
tx_data_in_0[8] => char_sent.OUTPUTSELECT
|
|
tx_data_in_0[8] => counter_aux.IN1
|
|
tx_data_in_0[8] => result_shift.IN0
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT
|
|
tx_data_in_0[8] => always1.IN1
|
|
process_data => next_state_tx.DATAA
|
|
process_data => next_state_tx.DATAA
|
|
process_data => next_state_tx.DATAA
|
|
process_data => next_state_tx.DATAA
|
|
process_data_0 => next_state_tx.DATAA
|
|
process_data_0 => next_state_tx.DATAA
|
|
gotfct_tx => gotfct_tx.IN1
|
|
send_fct_now => send_fct_now.IN1
|
|
tx_tcode_in[0] => ShiftRight0.IN14
|
|
tx_tcode_in[0] => last_timein_control_flag_tx.DATAB
|
|
tx_tcode_in[1] => ShiftRight0.IN13
|
|
tx_tcode_in[1] => last_timein_control_flag_tx.DATAB
|
|
tx_tcode_in[2] => ShiftRight0.IN12
|
|
tx_tcode_in[2] => last_timein_control_flag_tx.DATAB
|
|
tx_tcode_in[3] => ShiftRight0.IN11
|
|
tx_tcode_in[3] => last_timein_control_flag_tx.DATAB
|
|
tx_tcode_in[4] => ShiftRight0.IN10
|
|
tx_tcode_in[4] => last_timein_control_flag_tx.DATAB
|
|
tx_tcode_in[5] => ShiftRight0.IN9
|
|
tx_tcode_in[5] => last_timein_control_flag_tx.DATAB
|
|
tx_tcode_in[6] => ShiftRight0.IN8
|
|
tx_tcode_in[6] => last_timein_control_flag_tx.DATAB
|
|
tx_tcode_in[7] => ShiftRight0.IN7
|
|
tx_tcode_in[7] => last_timein_control_flag_tx.DATAB
|
|
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT
|
|
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT
|
|
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT
|
|
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT
|
|
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT
|
|
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT
|
|
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT
|
|
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT
|
|
tcode_rdy_trnsp => next_state_tx.DATAB
|
|
tcode_rdy_trnsp => next_state_tx.DATAB
|
|
tcode_rdy_trnsp => next_state_tx.DATAB
|
|
tcode_rdy_trnsp => next_state_tx.DATAB
|
|
tcode_rdy_trnsp => next_state_tx.DATAB
|
|
ready_tx_data <= ready_tx_data~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
ready_tx_timecode <= ready_tx_timecode~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
fct_great_than_zero <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
|
|
get_data <= get_data.DB_MAX_OUTPUT_PORT_TYPE
|
|
get_data_0 <= get_data_0.DB_MAX_OUTPUT_PORT_TYPE
|
|
tx_dout_e <= tx_dout_e~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
tx_sout_e <= tx_sout_e~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt
|
|
pclk_tx => clear_reg.CLK
|
|
pclk_tx => fct_counter_p[0]~reg0.CLK
|
|
pclk_tx => fct_counter_p[1]~reg0.CLK
|
|
pclk_tx => fct_counter_p[2]~reg0.CLK
|
|
pclk_tx => fct_counter_p[3]~reg0.CLK
|
|
pclk_tx => fct_counter_p[4]~reg0.CLK
|
|
pclk_tx => fct_counter_p[5]~reg0.CLK
|
|
pclk_tx => rec_b.CLK
|
|
pclk_tx => rec_a.CLK
|
pclk_tx => fct_counter_receive[0].CLK
|
pclk_tx => fct_counter_receive[0].CLK
|
pclk_tx => fct_counter_receive[1].CLK
|
pclk_tx => fct_counter_receive[1].CLK
|
pclk_tx => fct_counter_receive[2].CLK
|
pclk_tx => fct_counter_receive[2].CLK
|
pclk_tx => fct_counter_receive[3].CLK
|
pclk_tx => fct_counter_receive[3].CLK
|
pclk_tx => fct_counter_receive[4].CLK
|
pclk_tx => fct_counter_receive[4].CLK
|
pclk_tx => fct_counter_receive[5].CLK
|
pclk_tx => fct_counter_receive[5].CLK
|
pclk_tx => last_timein_control_flag_tx[0].CLK
|
pclk_tx => state_fct_p~1.DATAIN
|
pclk_tx => last_timein_control_flag_tx[1].CLK
|
pclk_tx => state_fct_receive~1.DATAIN
|
pclk_tx => last_timein_control_flag_tx[2].CLK
|
enable_tx => fct_counter_p.OUTPUTSELECT
|
pclk_tx => last_timein_control_flag_tx[3].CLK
|
enable_tx => fct_counter_p.OUTPUTSELECT
|
pclk_tx => last_timein_control_flag_tx[4].CLK
|
enable_tx => fct_counter_p.OUTPUTSELECT
|
pclk_tx => last_timein_control_flag_tx[5].CLK
|
enable_tx => fct_counter_p.OUTPUTSELECT
|
pclk_tx => last_timein_control_flag_tx[6].CLK
|
enable_tx => fct_counter_p.OUTPUTSELECT
|
pclk_tx => last_timein_control_flag_tx[7].CLK
|
enable_tx => fct_counter_p.OUTPUTSELECT
|
pclk_tx => txdata_flagctrl_tx_last[0].CLK
|
enable_tx => state_fct_p.OUTPUTSELECT
|
pclk_tx => txdata_flagctrl_tx_last[1].CLK
|
enable_tx => state_fct_p.OUTPUTSELECT
|
pclk_tx => txdata_flagctrl_tx_last[2].CLK
|
enable_tx => state_fct_p.OUTPUTSELECT
|
pclk_tx => txdata_flagctrl_tx_last[3].CLK
|
enable_tx => state_fct_p.OUTPUTSELECT
|
pclk_tx => txdata_flagctrl_tx_last[4].CLK
|
enable_tx => state_fct_p.OUTPUTSELECT
|
pclk_tx => txdata_flagctrl_tx_last[5].CLK
|
enable_tx => clear_reg.OUTPUTSELECT
|
pclk_tx => txdata_flagctrl_tx_last[6].CLK
|
enable_tx => fct_counter_receive.OUTPUTSELECT
|
pclk_tx => txdata_flagctrl_tx_last[7].CLK
|
enable_tx => fct_counter_receive.OUTPUTSELECT
|
pclk_tx => global_counter_transfer[0].CLK
|
enable_tx => fct_counter_receive.OUTPUTSELECT
|
pclk_tx => global_counter_transfer[1].CLK
|
enable_tx => fct_counter_receive.OUTPUTSELECT
|
pclk_tx => global_counter_transfer[2].CLK
|
enable_tx => fct_counter_receive.OUTPUTSELECT
|
pclk_tx => global_counter_transfer[3].CLK
|
enable_tx => fct_counter_receive.OUTPUTSELECT
|
pclk_tx => hold_time_code.CLK
|
enable_tx => state_fct_receive.OUTPUTSELECT
|
pclk_tx => hold_data.CLK
|
enable_tx => state_fct_receive.OUTPUTSELECT
|
pclk_tx => hold_fct.CLK
|
enable_tx => state_fct_receive.OUTPUTSELECT
|
pclk_tx => hold_null.CLK
|
enable_tx => state_fct_receive.OUTPUTSELECT
|
pclk_tx => ready_tx_timecode~reg0.CLK
|
enable_tx => state_fct_receive.OUTPUTSELECT
|
pclk_tx => ready_tx_data~reg0.CLK
|
enable_tx => rec_a.OUTPUTSELECT
|
pclk_tx => first_time.CLK
|
enable_tx => rec_b.OUTPUTSELECT
|
|
gotfct_tx => rec_a.DATAA
|
|
char_sent => Selector8.IN1
|
|
char_sent => fct_counter_p.OUTPUTSELECT
|
|
char_sent => fct_counter_p.OUTPUTSELECT
|
|
char_sent => fct_counter_p.OUTPUTSELECT
|
|
char_sent => fct_counter_p.OUTPUTSELECT
|
|
char_sent => fct_counter_p.OUTPUTSELECT
|
|
char_sent => fct_counter_p.OUTPUTSELECT
|
|
char_sent => Selector7.IN4
|
|
char_sent => Selector9.IN3
|
|
fct_counter_p[0] <= fct_counter_p[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
fct_counter_p[1] <= fct_counter_p[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
fct_counter_p[2] <= fct_counter_p[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
fct_counter_p[3] <= fct_counter_p[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
fct_counter_p[4] <= fct_counter_p[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
fct_counter_p[5] <= fct_counter_p[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd
|
|
pclk_tx => clear_reg_fct_flag.CLK
|
|
pclk_tx => fct_flag_p[0]~reg0.CLK
|
|
pclk_tx => fct_flag_p[1]~reg0.CLK
|
|
pclk_tx => fct_flag_p[2]~reg0.CLK
|
pclk_tx => fct_flag[0].CLK
|
pclk_tx => fct_flag[0].CLK
|
pclk_tx => fct_flag[1].CLK
|
pclk_tx => fct_flag[1].CLK
|
pclk_tx => fct_flag[2].CLK
|
pclk_tx => fct_flag[2].CLK
|
pclk_tx => timecode_s[0].CLK
|
pclk_tx => state_fct_send_p~1.DATAIN
|
pclk_tx => timecode_s[1].CLK
|
pclk_tx => state_fct_send~1.DATAIN
|
pclk_tx => timecode_s[2].CLK
|
enable_tx => clear_reg_fct_flag.ACLR
|
pclk_tx => timecode_s[3].CLK
|
enable_tx => fct_flag_p[0]~reg0.PRESET
|
pclk_tx => timecode_s[4].CLK
|
enable_tx => fct_flag_p[1]~reg0.PRESET
|
pclk_tx => timecode_s[5].CLK
|
enable_tx => fct_flag_p[2]~reg0.PRESET
|
pclk_tx => timecode_s[6].CLK
|
enable_tx => fct_flag.OUTPUTSELECT
|
pclk_tx => timecode_s[7].CLK
|
enable_tx => fct_flag.OUTPUTSELECT
|
pclk_tx => timecode_s[8].CLK
|
enable_tx => fct_flag.OUTPUTSELECT
|
pclk_tx => timecode_s[9].CLK
|
enable_tx => state_fct_send.OUTPUTSELECT
|
pclk_tx => timecode_s[10].CLK
|
enable_tx => state_fct_send.OUTPUTSELECT
|
pclk_tx => timecode_s[11].CLK
|
enable_tx => state_fct_send_p~3.DATAIN
|
pclk_tx => timecode_s[12].CLK
|
send_fct_now => fct_flag.OUTPUTSELECT
|
pclk_tx => tx_sout_e~reg0.CLK
|
send_fct_now => fct_flag.OUTPUTSELECT
|
pclk_tx => tx_dout_e~reg0.CLK
|
send_fct_now => fct_flag.OUTPUTSELECT
|
pclk_tx => state_tx~1.DATAIN
|
send_fct_now => next_state_fct_send_p.OUTPUTSELECT
|
pclk_tx => last_type~1.DATAIN
|
send_fct_now => next_state_fct_send_p.OUTPUTSELECT
|
data_tx_i[0] => tx_dout_data.DATAB
|
send_fct_now => fct_flag_p.OUTPUTSELECT
|
data_tx_i[0] => txdata_flagctrl_tx_last.DATAB
|
send_fct_now => fct_flag_p.OUTPUTSELECT
|
data_tx_i[0] => Equal11.IN0
|
send_fct_now => fct_flag_p.OUTPUTSELECT
|
data_tx_i[0] => Equal14.IN1
|
send_fct_now => clear_reg_fct_flag.OUTPUTSELECT
|
data_tx_i[1] => tx_dout_data.DATAB
|
send_fct_now => state_fct_send.DATAA
|
data_tx_i[1] => txdata_flagctrl_tx_last.DATAB
|
send_fct_now => state_fct_send.DATAA
|
data_tx_i[1] => Equal11.IN1
|
fct_sent => fct_flag_p.OUTPUTSELECT
|
data_tx_i[1] => Equal14.IN0
|
fct_sent => fct_flag_p.OUTPUTSELECT
|
data_tx_i[2] => tx_dout_data.DATAB
|
fct_sent => fct_flag_p.OUTPUTSELECT
|
data_tx_i[2] => txdata_flagctrl_tx_last.DATAB
|
fct_sent => Selector2.IN2
|
data_tx_i[3] => tx_dout_data.DATAB
|
fct_sent => always2.IN1
|
data_tx_i[3] => txdata_flagctrl_tx_last.DATAB
|
fct_sent => always2.IN1
|
data_tx_i[4] => tx_dout_data.DATAB
|
fct_sent => Selector1.IN2
|
data_tx_i[4] => txdata_flagctrl_tx_last.DATAB
|
fct_flag_p[0] <= fct_flag_p[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_tx_i[5] => tx_dout_data.DATAB
|
fct_flag_p[1] <= fct_flag_p[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_tx_i[5] => txdata_flagctrl_tx_last.DATAB
|
fct_flag_p[2] <= fct_flag_p[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_tx_i[6] => tx_dout_data.DATAB
|
|
data_tx_i[6] => txdata_flagctrl_tx_last.DATAB
|
|
data_tx_i[7] => tx_dout_data.DATAB
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd
|
data_tx_i[7] => txdata_flagctrl_tx_last.DATAB
|
pclk_tx => tx_tcode_in[0]~reg0.CLK
|
data_tx_i[8] => tx_dout_data.IN1
|
pclk_tx => tx_tcode_in[1]~reg0.CLK
|
data_tx_i[8] => tx_dout_data.IN1
|
pclk_tx => tx_tcode_in[2]~reg0.CLK
|
data_tx_i[8] => always3.IN1
|
pclk_tx => tx_tcode_in[3]~reg0.CLK
|
data_tx_i[8] => always3.IN1
|
pclk_tx => tx_tcode_in[4]~reg0.CLK
|
data_tx_i[8] => tx_dout_data.DATAB
|
pclk_tx => tx_tcode_in[5]~reg0.CLK
|
data_tx_i[8] => tx_dout_data.DATAB
|
pclk_tx => tx_tcode_in[6]~reg0.CLK
|
data_tx_i[8] => tx_dout_data.DATAB
|
pclk_tx => tx_tcode_in[7]~reg0.CLK
|
data_tx_i[8] => hold_data.OUTPUTSELECT
|
pclk_tx => tx_data_in_0[0]~reg0.CLK
|
data_tx_i[8] => ready_tx_data.OUTPUTSELECT
|
pclk_tx => tx_data_in_0[1]~reg0.CLK
|
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT
|
pclk_tx => tx_data_in_0[2]~reg0.CLK
|
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT
|
pclk_tx => tx_data_in_0[3]~reg0.CLK
|
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT
|
pclk_tx => tx_data_in_0[4]~reg0.CLK
|
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT
|
pclk_tx => tx_data_in_0[5]~reg0.CLK
|
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT
|
pclk_tx => tx_data_in_0[6]~reg0.CLK
|
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT
|
pclk_tx => tx_data_in_0[7]~reg0.CLK
|
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT
|
pclk_tx => tx_data_in_0[8]~reg0.CLK
|
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT
|
pclk_tx => tx_data_in[0]~reg0.CLK
|
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT
|
pclk_tx => tx_data_in[1]~reg0.CLK
|
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT
|
pclk_tx => tx_data_in[2]~reg0.CLK
|
data_tx_i[8] => block_sum.OUTPUTSELECT
|
pclk_tx => tx_data_in[3]~reg0.CLK
|
data_tx_i[8] => last_type.OUTPUTSELECT
|
pclk_tx => tx_data_in[4]~reg0.CLK
|
data_tx_i[8] => last_type.OUTPUTSELECT
|
pclk_tx => tx_data_in[5]~reg0.CLK
|
data_tx_i[8] => last_type.OUTPUTSELECT
|
pclk_tx => tx_data_in[6]~reg0.CLK
|
data_tx_i[8] => last_type.OUTPUTSELECT
|
pclk_tx => tx_data_in[7]~reg0.CLK
|
data_tx_i[8] => last_type.OUTPUTSELECT
|
pclk_tx => tx_data_in[8]~reg0.CLK
|
data_tx_i[8] => last_type.OUTPUTSELECT
|
pclk_tx => tcode_rdy_trnsp~reg0.CLK
|
data_tx_i[8] => hold_data.OUTPUTSELECT
|
pclk_tx => process_data_0~reg0.CLK
|
data_tx_i[8] => ready_tx_data.OUTPUTSELECT
|
pclk_tx => process_data~reg0.CLK
|
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT
|
enable_tx => process_data.OUTPUTSELECT
|
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT
|
enable_tx => process_data_0.OUTPUTSELECT
|
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT
|
enable_tx => tcode_rdy_trnsp.OUTPUTSELECT
|
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT
|
enable_tx => tx_data_in.OUTPUTSELECT
|
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
enable_tx => tx_data_in.OUTPUTSELECT
|
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
enable_tx => tx_data_in.OUTPUTSELECT
|
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
enable_tx => tx_data_in.OUTPUTSELECT
|
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
enable_tx => tx_data_in.OUTPUTSELECT
|
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
enable_tx => tx_data_in.OUTPUTSELECT
|
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
enable_tx => tx_data_in.OUTPUTSELECT
|
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
enable_tx => tx_data_in.OUTPUTSELECT
|
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT
|
enable_tx => tx_data_in.OUTPUTSELECT
|
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT
|
enable_tx => tx_data_in_0.OUTPUTSELECT
|
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT
|
enable_tx => tx_data_in_0.OUTPUTSELECT
|
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT
|
enable_tx => tx_data_in_0.OUTPUTSELECT
|
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT
|
enable_tx => tx_data_in_0.OUTPUTSELECT
|
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT
|
enable_tx => tx_data_in_0.OUTPUTSELECT
|
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT
|
enable_tx => tx_data_in_0.OUTPUTSELECT
|
data_tx_i[8] => block_sum.OUTPUTSELECT
|
enable_tx => tx_data_in_0.OUTPUTSELECT
|
data_tx_i[8] => last_type.OUTPUTSELECT
|
enable_tx => tx_data_in_0.OUTPUTSELECT
|
data_tx_i[8] => last_type.OUTPUTSELECT
|
enable_tx => tx_data_in_0.OUTPUTSELECT
|
data_tx_i[8] => last_type.OUTPUTSELECT
|
enable_tx => tx_tcode_in.OUTPUTSELECT
|
data_tx_i[8] => last_type.OUTPUTSELECT
|
enable_tx => tx_tcode_in.OUTPUTSELECT
|
data_tx_i[8] => last_type.OUTPUTSELECT
|
enable_tx => tx_tcode_in.OUTPUTSELECT
|
data_tx_i[8] => last_type.OUTPUTSELECT
|
enable_tx => tx_tcode_in.OUTPUTSELECT
|
data_tx_i[8] => always3.IN1
|
enable_tx => tx_tcode_in.OUTPUTSELECT
|
data_tx_i[8] => always3.IN1
|
enable_tx => tx_tcode_in.OUTPUTSELECT
|
data_tx_i[8] => always3.IN1
|
enable_tx => tx_tcode_in.OUTPUTSELECT
|
data_tx_i[8] => always3.IN1
|
enable_tx => tx_tcode_in.OUTPUTSELECT
|
data_tx_i[8] => always3.IN1
|
get_data => always0.IN1
|
data_tx_i[8] => always3.IN1
|
get_data_0 => always0.IN1
|
data_tx_i[8] => always3.IN1
|
timecode_tx_i[0] => tx_tcode_in.DATAB
|
data_tx_i[8] => always3.IN1
|
timecode_tx_i[1] => tx_tcode_in.DATAB
|
data_tx_i[8] => always3.IN1
|
timecode_tx_i[2] => tx_tcode_in.DATAB
|
data_tx_i[8] => always3.IN0
|
timecode_tx_i[3] => tx_tcode_in.DATAB
|
data_tx_i[8] => always3.IN0
|
timecode_tx_i[4] => tx_tcode_in.DATAB
|
data_tx_i[8] => always3.IN0
|
timecode_tx_i[5] => tx_tcode_in.DATAB
|
data_tx_i[8] => always3.IN0
|
timecode_tx_i[6] => tx_tcode_in.DATAB
|
data_tx_i[8] => tx_dout_data.DATAB
|
timecode_tx_i[7] => tx_tcode_in.DATAB
|
data_tx_i[8] => always3.IN0
|
tickin_tx => tx_tcode_in.OUTPUTSELECT
|
data_tx_i[8] => tx_dout_data.DATAB
|
tickin_tx => tx_tcode_in.OUTPUTSELECT
|
data_tx_i[8] => always3.IN0
|
tickin_tx => tx_tcode_in.OUTPUTSELECT
|
txwrite_tx => always7.IN1
|
tickin_tx => tx_tcode_in.OUTPUTSELECT
|
timecode_tx_i[0] => timecode_s.DATAB
|
tickin_tx => tx_tcode_in.OUTPUTSELECT
|
timecode_tx_i[0] => last_timein_control_flag_tx.DATAA
|
tickin_tx => tx_tcode_in.OUTPUTSELECT
|
timecode_tx_i[1] => timecode_s.DATAB
|
tickin_tx => tx_tcode_in.OUTPUTSELECT
|
timecode_tx_i[1] => last_timein_control_flag_tx.DATAA
|
tickin_tx => tx_tcode_in.OUTPUTSELECT
|
timecode_tx_i[2] => timecode_s.DATAB
|
tickin_tx => tcode_rdy_trnsp.DATAA
|
timecode_tx_i[2] => last_timein_control_flag_tx.DATAA
|
data_tx_i[0] => tx_data_in.DATAB
|
timecode_tx_i[3] => timecode_s.DATAB
|
data_tx_i[0] => tx_data_in_0.DATAB
|
timecode_tx_i[3] => last_timein_control_flag_tx.DATAA
|
data_tx_i[1] => tx_data_in.DATAB
|
timecode_tx_i[4] => timecode_s.DATAB
|
data_tx_i[1] => tx_data_in_0.DATAB
|
timecode_tx_i[4] => last_timein_control_flag_tx.DATAA
|
data_tx_i[2] => tx_data_in.DATAB
|
timecode_tx_i[5] => timecode_s.DATAB
|
data_tx_i[2] => tx_data_in_0.DATAB
|
timecode_tx_i[5] => last_timein_control_flag_tx.DATAA
|
data_tx_i[3] => tx_data_in.DATAB
|
timecode_tx_i[6] => timecode_s.DATAB
|
data_tx_i[3] => tx_data_in_0.DATAB
|
timecode_tx_i[6] => last_timein_control_flag_tx.DATAA
|
data_tx_i[4] => tx_data_in.DATAB
|
timecode_tx_i[7] => timecode_s.DATAB
|
data_tx_i[4] => tx_data_in_0.DATAB
|
timecode_tx_i[7] => last_timein_control_flag_tx.DATAA
|
data_tx_i[5] => tx_data_in.DATAB
|
tickin_tx => always7.IN1
|
data_tx_i[5] => tx_data_in_0.DATAB
|
enable_tx => always7.IN0
|
data_tx_i[6] => tx_data_in.DATAB
|
enable_tx => always7.IN1
|
data_tx_i[6] => tx_data_in_0.DATAB
|
enable_tx => last_tx_sout.ACLR
|
data_tx_i[7] => tx_data_in.DATAB
|
enable_tx => last_tx_dout.ACLR
|
data_tx_i[7] => tx_data_in_0.DATAB
|
enable_tx => block_sum_fct_send.ACLR
|
data_tx_i[8] => tx_data_in.DATAB
|
enable_tx => block_sum.ACLR
|
data_tx_i[8] => tx_data_in_0.DATAB
|
enable_tx => fct_counter_receive[0].ACLR
|
txwrite_tx => process_data_en.IN0
|
enable_tx => fct_counter_receive[1].ACLR
|
fct_counter_p => process_data_en.IN1
|
enable_tx => fct_counter_receive[2].ACLR
|
tx_data_in[0] <= tx_data_in[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => fct_counter_receive[3].ACLR
|
tx_data_in[1] <= tx_data_in[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => fct_counter_receive[4].ACLR
|
tx_data_in[2] <= tx_data_in[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => fct_counter_receive[5].ACLR
|
tx_data_in[3] <= tx_data_in[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => last_timein_control_flag_tx[0].ACLR
|
tx_data_in[4] <= tx_data_in[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => last_timein_control_flag_tx[1].ACLR
|
tx_data_in[5] <= tx_data_in[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => last_timein_control_flag_tx[2].ACLR
|
tx_data_in[6] <= tx_data_in[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => last_timein_control_flag_tx[3].ACLR
|
tx_data_in[7] <= tx_data_in[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => last_timein_control_flag_tx[4].ACLR
|
tx_data_in[8] <= tx_data_in[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => last_timein_control_flag_tx[5].ACLR
|
tx_data_in_0[0] <= tx_data_in_0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => last_timein_control_flag_tx[6].ACLR
|
tx_data_in_0[1] <= tx_data_in_0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => last_timein_control_flag_tx[7].ACLR
|
tx_data_in_0[2] <= tx_data_in_0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => txdata_flagctrl_tx_last[0].ACLR
|
tx_data_in_0[3] <= tx_data_in_0[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => txdata_flagctrl_tx_last[1].ACLR
|
tx_data_in_0[4] <= tx_data_in_0[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => txdata_flagctrl_tx_last[2].ACLR
|
tx_data_in_0[5] <= tx_data_in_0[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => txdata_flagctrl_tx_last[3].ACLR
|
tx_data_in_0[6] <= tx_data_in_0[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => txdata_flagctrl_tx_last[4].ACLR
|
tx_data_in_0[7] <= tx_data_in_0[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => txdata_flagctrl_tx_last[5].ACLR
|
tx_data_in_0[8] <= tx_data_in_0[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => txdata_flagctrl_tx_last[6].ACLR
|
process_data <= process_data~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => txdata_flagctrl_tx_last[7].ACLR
|
process_data_0 <= process_data_0~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => global_counter_transfer[0].ACLR
|
tx_tcode_in[0] <= tx_tcode_in[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => global_counter_transfer[1].ACLR
|
tx_tcode_in[1] <= tx_tcode_in[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => global_counter_transfer[2].ACLR
|
tx_tcode_in[2] <= tx_tcode_in[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => global_counter_transfer[3].ACLR
|
tx_tcode_in[3] <= tx_tcode_in[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => hold_time_code.ACLR
|
tx_tcode_in[4] <= tx_tcode_in[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => hold_data.ACLR
|
tx_tcode_in[5] <= tx_tcode_in[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => hold_fct.ACLR
|
tx_tcode_in[6] <= tx_tcode_in[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => hold_null.ACLR
|
tx_tcode_in[7] <= tx_tcode_in[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => ready_tx_timecode~reg0.ACLR
|
tcode_rdy_trnsp <= tcode_rdy_trnsp~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
enable_tx => ready_tx_data~reg0.ACLR
|
|
enable_tx => first_time.PRESET
|
|
enable_tx => fct_flag[0].PRESET
|
|
enable_tx => fct_flag[1].PRESET
|
|
enable_tx => fct_flag[2].PRESET
|
|
enable_tx => timecode_s[0].ACLR
|
|
enable_tx => timecode_s[1].ACLR
|
|
enable_tx => timecode_s[2].ACLR
|
|
enable_tx => timecode_s[3].ACLR
|
|
enable_tx => timecode_s[4].ACLR
|
|
enable_tx => timecode_s[5].ACLR
|
|
enable_tx => timecode_s[6].ACLR
|
|
enable_tx => timecode_s[7].ACLR
|
|
enable_tx => timecode_s[8].ACLR
|
|
enable_tx => timecode_s[9].ACLR
|
|
enable_tx => timecode_s[10].PRESET
|
|
enable_tx => timecode_s[11].PRESET
|
|
enable_tx => timecode_s[12].PRESET
|
|
enable_tx => tx_sout_e~reg0.ACLR
|
|
enable_tx => tx_dout_e~reg0.ACLR
|
|
enable_tx => tx_sout.OUTPUTSELECT
|
|
enable_tx => state_tx~3.DATAIN
|
|
enable_tx => last_type~3.DATAIN
|
|
send_null_tx => always7.IN1
|
|
send_null_tx => always7.IN0
|
|
send_fct_tx => always7.IN1
|
|
send_fct_tx => always7.IN1
|
|
send_fct_tx => always7.IN1
|
|
gotfct_tx => fct_counter[5].OUTPUTSELECT
|
|
gotfct_tx => fct_counter[4].OUTPUTSELECT
|
|
gotfct_tx => fct_counter[3].OUTPUTSELECT
|
|
gotfct_tx => fct_counter[2].OUTPUTSELECT
|
|
gotfct_tx => fct_counter[1].OUTPUTSELECT
|
|
gotfct_tx => fct_counter[0].OUTPUTSELECT
|
|
gotfct_tx => always10.IN1
|
|
gotfct_tx => block_sum.OUTPUTSELECT
|
|
send_fct_now => fct_send[2].OUTPUTSELECT
|
|
send_fct_now => fct_send[1].OUTPUTSELECT
|
|
send_fct_now => fct_send[0].OUTPUTSELECT
|
|
send_fct_now => always10.IN1
|
|
send_fct_now => block_sum_fct_send.OUTPUTSELECT
|
|
tx_dout_e <= tx_dout_e~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
tx_sout_e <= tx_sout_e~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
ready_tx_data <= ready_tx_data~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
ready_tx_timecode <= ready_tx_timecode~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data
|
clock => block_read.CLK
|
clock => clock.IN1
|
clock => open_slot_fct~reg0.CLK
|
reset => reset.IN1
|
|
wr_en => always1.IN1
|
|
wr_en => Selector4.IN2
|
|
wr_en => next_state_data_write.10.DATAB
|
|
rd_en => always2.IN1
|
|
rd_en => always5.IN1
|
|
rd_en => always5.IN0
|
|
rd_en => rd_ptr.OUTPUTSELECT
|
|
rd_en => rd_ptr.OUTPUTSELECT
|
|
rd_en => rd_ptr.OUTPUTSELECT
|
|
rd_en => rd_ptr.OUTPUTSELECT
|
|
rd_en => rd_ptr.OUTPUTSELECT
|
|
rd_en => rd_ptr.OUTPUTSELECT
|
|
rd_en => Selector6.IN2
|
|
rd_en => next_state_data_read.10.DATAB
|
|
data_in[0] => data_in[0].IN1
|
|
data_in[1] => data_in[1].IN1
|
|
data_in[2] => data_in[2].IN1
|
|
data_in[3] => data_in[3].IN1
|
|
data_in[4] => data_in[4].IN1
|
|
data_in[5] => data_in[5].IN1
|
|
data_in[6] => data_in[6].IN1
|
|
data_in[7] => data_in[7].IN1
|
|
data_in[8] => data_in[8].IN1
|
|
f_full <= f_full~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
f_empty <= f_empty~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
open_slot_fct <= open_slot_fct~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
overflow_credit_error <= overflow_credit_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_out[0] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[1] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[2] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[3] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[4] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[5] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[6] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[7] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[8] <= mem_data:mem_dta_fifo_tx.data_out
|
|
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter[4] <= counter[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter[5] <= counter[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx
|
clock => data_out[0]~reg0.CLK
|
clock => data_out[0]~reg0.CLK
|
clock => data_out[1]~reg0.CLK
|
clock => data_out[1]~reg0.CLK
|
clock => data_out[2]~reg0.CLK
|
clock => data_out[2]~reg0.CLK
|
clock => data_out[3]~reg0.CLK
|
clock => data_out[3]~reg0.CLK
|
clock => data_out[4]~reg0.CLK
|
clock => data_out[4]~reg0.CLK
|
clock => data_out[5]~reg0.CLK
|
clock => data_out[5]~reg0.CLK
|
clock => data_out[6]~reg0.CLK
|
clock => data_out[6]~reg0.CLK
|
clock => data_out[7]~reg0.CLK
|
clock => data_out[7]~reg0.CLK
|
clock => data_out[8]~reg0.CLK
|
clock => data_out[8]~reg0.CLK
|
clock => rd_ptr[0].CLK
|
|
clock => rd_ptr[1].CLK
|
|
clock => rd_ptr[2].CLK
|
|
clock => rd_ptr[3].CLK
|
|
clock => rd_ptr[4].CLK
|
|
clock => rd_ptr[5].CLK
|
|
clock => credit_counter[0].CLK
|
|
clock => credit_counter[1].CLK
|
|
clock => credit_counter[2].CLK
|
|
clock => credit_counter[3].CLK
|
|
clock => credit_counter[4].CLK
|
|
clock => credit_counter[5].CLK
|
|
clock => counter[0]~reg0.CLK
|
|
clock => counter[1]~reg0.CLK
|
|
clock => counter[2]~reg0.CLK
|
|
clock => counter[3]~reg0.CLK
|
|
clock => counter[4]~reg0.CLK
|
|
clock => counter[5]~reg0.CLK
|
|
clock => f_empty~reg0.CLK
|
|
clock => f_full~reg0.CLK
|
|
clock => overflow_credit_error~reg0.CLK
|
|
clock => block_write.CLK
|
|
clock => mem[63][0].CLK
|
clock => mem[63][0].CLK
|
clock => mem[63][1].CLK
|
clock => mem[63][1].CLK
|
clock => mem[63][2].CLK
|
clock => mem[63][2].CLK
|
clock => mem[63][3].CLK
|
clock => mem[63][3].CLK
|
clock => mem[63][4].CLK
|
clock => mem[63][4].CLK
|
| Line 167932... |
Line 168450... |
clock => mem[0][4].CLK
|
clock => mem[0][4].CLK
|
clock => mem[0][5].CLK
|
clock => mem[0][5].CLK
|
clock => mem[0][6].CLK
|
clock => mem[0][6].CLK
|
clock => mem[0][7].CLK
|
clock => mem[0][7].CLK
|
clock => mem[0][8].CLK
|
clock => mem[0][8].CLK
|
clock => wr_ptr[0].CLK
|
|
clock => wr_ptr[1].CLK
|
|
clock => wr_ptr[2].CLK
|
|
clock => wr_ptr[3].CLK
|
|
clock => wr_ptr[4].CLK
|
|
clock => wr_ptr[5].CLK
|
|
reset => overflow_credit_error~reg0.ACLR
|
|
reset => block_write.ACLR
|
|
reset => mem[63][0].ACLR
|
reset => mem[63][0].ACLR
|
reset => mem[63][1].ACLR
|
reset => mem[63][1].ACLR
|
reset => mem[63][2].ACLR
|
reset => mem[63][2].ACLR
|
reset => mem[63][3].ACLR
|
reset => mem[63][3].ACLR
|
reset => mem[63][4].ACLR
|
reset => mem[63][4].ACLR
|
| Line 168516... |
Line 169026... |
reset => mem[0][4].ACLR
|
reset => mem[0][4].ACLR
|
reset => mem[0][5].ACLR
|
reset => mem[0][5].ACLR
|
reset => mem[0][6].ACLR
|
reset => mem[0][6].ACLR
|
reset => mem[0][7].ACLR
|
reset => mem[0][7].ACLR
|
reset => mem[0][8].ACLR
|
reset => mem[0][8].ACLR
|
reset => wr_ptr[0].ACLR
|
|
reset => wr_ptr[1].ACLR
|
|
reset => wr_ptr[2].ACLR
|
|
reset => wr_ptr[3].ACLR
|
|
reset => wr_ptr[4].ACLR
|
|
reset => wr_ptr[5].ACLR
|
|
reset => block_read.ACLR
|
|
reset => open_slot_fct~reg0.ACLR
|
|
reset => data_out[0]~reg0.ACLR
|
reset => data_out[0]~reg0.ACLR
|
reset => data_out[1]~reg0.ACLR
|
reset => data_out[1]~reg0.ACLR
|
reset => data_out[2]~reg0.ACLR
|
reset => data_out[2]~reg0.ACLR
|
reset => data_out[3]~reg0.ACLR
|
reset => data_out[3]~reg0.ACLR
|
reset => data_out[4]~reg0.ACLR
|
reset => data_out[4]~reg0.ACLR
|
reset => data_out[5]~reg0.ACLR
|
reset => data_out[5]~reg0.ACLR
|
reset => data_out[6]~reg0.ACLR
|
reset => data_out[6]~reg0.ACLR
|
reset => data_out[7]~reg0.ACLR
|
reset => data_out[7]~reg0.ACLR
|
reset => data_out[8]~reg0.ACLR
|
reset => data_out[8]~reg0.ACLR
|
reset => rd_ptr[0].ACLR
|
data_in[0] => mem[0][0].DATAIN
|
reset => rd_ptr[1].ACLR
|
data_in[0] => mem[1][0].DATAIN
|
reset => rd_ptr[2].ACLR
|
data_in[0] => mem[2][0].DATAIN
|
reset => rd_ptr[3].ACLR
|
data_in[0] => mem[3][0].DATAIN
|
reset => rd_ptr[4].ACLR
|
data_in[0] => mem[4][0].DATAIN
|
reset => rd_ptr[5].ACLR
|
data_in[0] => mem[5][0].DATAIN
|
reset => credit_counter[0].PRESET
|
data_in[0] => mem[6][0].DATAIN
|
reset => credit_counter[1].PRESET
|
data_in[0] => mem[7][0].DATAIN
|
reset => credit_counter[2].PRESET
|
data_in[0] => mem[8][0].DATAIN
|
reset => credit_counter[3].ACLR
|
data_in[0] => mem[9][0].DATAIN
|
reset => credit_counter[4].PRESET
|
data_in[0] => mem[10][0].DATAIN
|
reset => credit_counter[5].PRESET
|
data_in[0] => mem[11][0].DATAIN
|
reset => counter[0]~reg0.ACLR
|
data_in[0] => mem[12][0].DATAIN
|
reset => counter[1]~reg0.ACLR
|
data_in[0] => mem[13][0].DATAIN
|
reset => counter[2]~reg0.ACLR
|
data_in[0] => mem[14][0].DATAIN
|
reset => counter[3]~reg0.ACLR
|
data_in[0] => mem[15][0].DATAIN
|
reset => counter[4]~reg0.ACLR
|
data_in[0] => mem[16][0].DATAIN
|
reset => counter[5]~reg0.ACLR
|
data_in[0] => mem[17][0].DATAIN
|
reset => f_empty~reg0.PRESET
|
data_in[0] => mem[18][0].DATAIN
|
reset => f_full~reg0.ACLR
|
data_in[0] => mem[19][0].DATAIN
|
wr_en => always0.IN1
|
data_in[0] => mem[20][0].DATAIN
|
wr_en => always1.IN1
|
data_in[0] => mem[21][0].DATAIN
|
wr_en => block_write.OUTPUTSELECT
|
data_in[0] => mem[22][0].DATAIN
|
wr_en => wr_ptr.OUTPUTSELECT
|
data_in[0] => mem[23][0].DATAIN
|
wr_en => wr_ptr.OUTPUTSELECT
|
data_in[0] => mem[24][0].DATAIN
|
wr_en => wr_ptr.OUTPUTSELECT
|
data_in[0] => mem[25][0].DATAIN
|
wr_en => wr_ptr.OUTPUTSELECT
|
data_in[0] => mem[26][0].DATAIN
|
wr_en => wr_ptr.OUTPUTSELECT
|
data_in[0] => mem[27][0].DATAIN
|
wr_en => wr_ptr.OUTPUTSELECT
|
data_in[0] => mem[28][0].DATAIN
|
rd_en => always1.IN1
|
data_in[0] => mem[29][0].DATAIN
|
rd_en => block_read.OUTPUTSELECT
|
data_in[0] => mem[30][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[31][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[32][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[33][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[34][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[35][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[36][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[37][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[38][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[39][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[40][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[41][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[42][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[43][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[44][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[45][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[46][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[47][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[48][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[49][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[50][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[51][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[52][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[53][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[54][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[55][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[56][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[57][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[58][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[59][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[60][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[61][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[62][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[63][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[0][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[1][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[2][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[3][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[4][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[5][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[6][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[7][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[8][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[9][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[10][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[11][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[12][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[13][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[14][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[15][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[16][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[17][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[18][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[19][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[20][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[21][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[22][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[23][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[24][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[25][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[26][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[27][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[28][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[29][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[30][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[31][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[32][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[33][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[34][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[35][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[36][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[37][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[38][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[39][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[40][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[41][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[42][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[43][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[44][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[45][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[46][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[47][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[48][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[49][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[50][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[51][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[52][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[53][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[54][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[55][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[56][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[57][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[58][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[59][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[60][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[61][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[62][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[63][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[0][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[1][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[2][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[3][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[4][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[5][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[6][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[7][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[8][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[9][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[10][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[11][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[12][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[13][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[14][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[15][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[16][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[17][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[18][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[19][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[20][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[21][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[22][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[23][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[24][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[25][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[26][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[27][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[28][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[29][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[30][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[31][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[32][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[33][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[34][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[35][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[36][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[37][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[38][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[39][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[40][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[41][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[42][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[43][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[44][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[45][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[46][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[47][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[48][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[49][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[50][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[51][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[52][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[53][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[54][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[55][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[56][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[57][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[58][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[59][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[60][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[61][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[62][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[63][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[0][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[1][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[2][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[3][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[4][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[5][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[6][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[7][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[8][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[9][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[10][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[11][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[12][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[13][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[14][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[15][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[16][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[17][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[18][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[19][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[20][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[21][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[22][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[23][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[24][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[25][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[26][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[27][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[28][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[29][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[30][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[31][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[32][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[33][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[34][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[35][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[36][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[37][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[38][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[39][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[40][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[41][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[42][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[43][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[44][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[45][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[46][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[47][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[48][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[49][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[50][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[51][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[52][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[53][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[54][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[55][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[56][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[57][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[58][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[59][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[60][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[61][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[62][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[63][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[0][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[1][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[2][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[3][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[4][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[5][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[6][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[7][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[8][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[9][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[10][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[11][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[12][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[13][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[14][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[15][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[16][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[17][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[18][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[19][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[20][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[21][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[22][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[23][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[24][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[25][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[26][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[27][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[28][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[29][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[30][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[31][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[32][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[33][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[34][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[35][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[36][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[37][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[38][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[39][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[40][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[41][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[42][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[43][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[44][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[45][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[46][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[47][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[48][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[49][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[50][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[51][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[52][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[53][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[54][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[55][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[56][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[57][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[58][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[59][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[60][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[61][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[62][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[63][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[0][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[1][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[2][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[3][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[4][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[5][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[6][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[7][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[8][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[9][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[10][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[11][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[12][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[13][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[14][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[15][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[16][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[17][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[18][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[19][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[20][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[21][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[22][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[23][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[24][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[25][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[26][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[27][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[28][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[29][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[30][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[31][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[32][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[33][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[34][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[35][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[36][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[37][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[38][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[39][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[40][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[41][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[42][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[43][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[44][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[45][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[46][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[47][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[48][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[49][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[50][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[51][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[52][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[53][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[54][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[55][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[56][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[57][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[58][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[59][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[60][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[61][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[62][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[63][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[0][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[1][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[2][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[3][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[4][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[5][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[6][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[7][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[8][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[9][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[10][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[11][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[12][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[13][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[14][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[15][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[16][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[17][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[18][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[19][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[20][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[21][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[22][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[23][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[24][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[25][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[26][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[27][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[28][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[29][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[30][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[31][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[32][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[33][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[34][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[35][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[36][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[37][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[38][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[39][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[40][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[41][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[42][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[43][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[44][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[45][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[46][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[47][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[48][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[49][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[50][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[51][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[52][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[53][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[54][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[55][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[56][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[57][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[58][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[59][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[60][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[61][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[62][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[63][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[0][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[1][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[2][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[3][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[4][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[5][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[6][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[7][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[8][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[9][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[10][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[11][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[12][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[13][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[14][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[15][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[16][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[17][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[18][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[19][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[20][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[21][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[22][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[23][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[24][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[25][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[26][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[27][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[28][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[29][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[30][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[31][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[32][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[33][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[34][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[35][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[36][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[37][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[38][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[39][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[40][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[41][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[42][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[43][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[44][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[45][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[46][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[47][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[48][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[49][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[50][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[51][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[52][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[53][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[54][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[55][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[56][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[57][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[58][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[59][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[60][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[61][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[62][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[63][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[0][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[1][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[2][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[3][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[4][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[5][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[6][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[7][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[8][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[9][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[10][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[11][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[12][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[13][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[14][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[15][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[16][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[17][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[18][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[19][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[20][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[21][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[22][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[23][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[24][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[25][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[26][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[27][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[28][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[29][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[30][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[31][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[32][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[33][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[34][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[35][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[36][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[37][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[38][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[39][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[40][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[41][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[42][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[43][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[44][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[45][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[46][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[47][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[48][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[49][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[50][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[51][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[52][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[53][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[54][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[55][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[56][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[57][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[58][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[59][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[60][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[61][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[62][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[63][8].DATAIN
|
data_in[8] => mem.DATAB
|
wr_ptr[0] => Decoder0.IN5
|
data_in[8] => mem.DATAB
|
wr_ptr[1] => Decoder0.IN4
|
data_in[8] => mem.DATAB
|
wr_ptr[2] => Decoder0.IN3
|
data_in[8] => mem.DATAB
|
wr_ptr[3] => Decoder0.IN2
|
data_in[8] => mem.DATAB
|
wr_ptr[4] => Decoder0.IN1
|
data_in[8] => mem.DATAB
|
wr_ptr[5] => Decoder0.IN0
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux0.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux1.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux2.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux3.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux4.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux5.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux6.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux7.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux8.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux0.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux1.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux2.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux3.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux4.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux5.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux6.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux7.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux8.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[2] => Mux0.IN3
|
data_in[8] => mem.DATAB
|
rd_ptr[2] => Mux1.IN3
|
data_in[8] => mem.DATAB
|
rd_ptr[2] => Mux2.IN3
|
data_in[8] => mem.DATAB
|
rd_ptr[2] => Mux3.IN3
|
data_in[8] => mem.DATAB
|
rd_ptr[2] => Mux4.IN3
|
data_in[8] => mem.DATAB
|
rd_ptr[2] => Mux5.IN3
|
data_in[8] => mem.DATAB
|
rd_ptr[2] => Mux6.IN3
|
f_full <= f_full~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rd_ptr[2] => Mux7.IN3
|
f_empty <= f_empty~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rd_ptr[2] => Mux8.IN3
|
open_slot_fct <= open_slot_fct~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rd_ptr[3] => Mux0.IN2
|
overflow_credit_error <= overflow_credit_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rd_ptr[3] => Mux1.IN2
|
|
rd_ptr[3] => Mux2.IN2
|
|
rd_ptr[3] => Mux3.IN2
|
|
rd_ptr[3] => Mux4.IN2
|
|
rd_ptr[3] => Mux5.IN2
|
|
rd_ptr[3] => Mux6.IN2
|
|
rd_ptr[3] => Mux7.IN2
|
|
rd_ptr[3] => Mux8.IN2
|
|
rd_ptr[4] => Mux0.IN1
|
|
rd_ptr[4] => Mux1.IN1
|
|
rd_ptr[4] => Mux2.IN1
|
|
rd_ptr[4] => Mux3.IN1
|
|
rd_ptr[4] => Mux4.IN1
|
|
rd_ptr[4] => Mux5.IN1
|
|
rd_ptr[4] => Mux6.IN1
|
|
rd_ptr[4] => Mux7.IN1
|
|
rd_ptr[4] => Mux8.IN1
|
|
rd_ptr[5] => Mux0.IN0
|
|
rd_ptr[5] => Mux1.IN0
|
|
rd_ptr[5] => Mux2.IN0
|
|
rd_ptr[5] => Mux3.IN0
|
|
rd_ptr[5] => Mux4.IN0
|
|
rd_ptr[5] => Mux5.IN0
|
|
rd_ptr[5] => Mux6.IN0
|
|
rd_ptr[5] => Mux7.IN0
|
|
rd_ptr[5] => Mux8.IN0
|
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data
|
|
clock => clock.IN1
|
|
reset => reset.IN1
|
|
wr_en => always0.IN1
|
|
wr_en => Selector1.IN2
|
|
wr_en => next_state_data_write.10.DATAB
|
|
rd_en => always4.IN1
|
|
rd_en => Selector4.IN3
|
|
rd_en => always3.IN0
|
|
rd_en => next_state_data_read.11.DATAB
|
|
data_in[0] => data_in[0].IN1
|
|
data_in[1] => data_in[1].IN1
|
|
data_in[2] => data_in[2].IN1
|
|
data_in[3] => data_in[3].IN1
|
|
data_in[4] => data_in[4].IN1
|
|
data_in[5] => data_in[5].IN1
|
|
data_in[6] => data_in[6].IN1
|
|
data_in[7] => data_in[7].IN1
|
|
data_in[8] => data_in[8].IN1
|
|
f_full <= f_full~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
write_tx <= write_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
f_empty <= f_empty~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_out[0] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[1] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[2] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[3] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[4] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[5] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[6] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[7] <= mem_data:mem_dta_fifo_tx.data_out
|
|
data_out[8] <= mem_data:mem_dta_fifo_tx.data_out
|
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
counter[4] <= counter[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
counter[4] <= counter[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
counter[5] <= counter[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
counter[5] <= counter[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx
|
clock => block_read.CLK
|
|
clock => write_tx~reg0.CLK
|
|
clock => data_out[0]~reg0.CLK
|
clock => data_out[0]~reg0.CLK
|
clock => data_out[1]~reg0.CLK
|
clock => data_out[1]~reg0.CLK
|
clock => data_out[2]~reg0.CLK
|
clock => data_out[2]~reg0.CLK
|
clock => data_out[3]~reg0.CLK
|
clock => data_out[3]~reg0.CLK
|
clock => data_out[4]~reg0.CLK
|
clock => data_out[4]~reg0.CLK
|
clock => data_out[5]~reg0.CLK
|
clock => data_out[5]~reg0.CLK
|
clock => data_out[6]~reg0.CLK
|
clock => data_out[6]~reg0.CLK
|
clock => data_out[7]~reg0.CLK
|
clock => data_out[7]~reg0.CLK
|
clock => data_out[8]~reg0.CLK
|
clock => data_out[8]~reg0.CLK
|
clock => rd_ptr[0].CLK
|
|
clock => rd_ptr[1].CLK
|
|
clock => rd_ptr[2].CLK
|
|
clock => rd_ptr[3].CLK
|
|
clock => rd_ptr[4].CLK
|
|
clock => rd_ptr[5].CLK
|
|
clock => counter[0]~reg0.CLK
|
|
clock => counter[1]~reg0.CLK
|
|
clock => counter[2]~reg0.CLK
|
|
clock => counter[3]~reg0.CLK
|
|
clock => counter[4]~reg0.CLK
|
|
clock => counter[5]~reg0.CLK
|
|
clock => f_empty~reg0.CLK
|
|
clock => f_full~reg0.CLK
|
|
clock => block_write.CLK
|
|
clock => wr_ptr[0].CLK
|
|
clock => wr_ptr[1].CLK
|
|
clock => wr_ptr[2].CLK
|
|
clock => wr_ptr[3].CLK
|
|
clock => wr_ptr[4].CLK
|
|
clock => wr_ptr[5].CLK
|
|
clock => mem[63][0].CLK
|
clock => mem[63][0].CLK
|
clock => mem[63][1].CLK
|
clock => mem[63][1].CLK
|
clock => mem[63][2].CLK
|
clock => mem[63][2].CLK
|
clock => mem[63][3].CLK
|
clock => mem[63][3].CLK
|
clock => mem[63][4].CLK
|
clock => mem[63][4].CLK
|
| Line 169770... |
Line 170307... |
clock => mem[0][4].CLK
|
clock => mem[0][4].CLK
|
clock => mem[0][5].CLK
|
clock => mem[0][5].CLK
|
clock => mem[0][6].CLK
|
clock => mem[0][6].CLK
|
clock => mem[0][7].CLK
|
clock => mem[0][7].CLK
|
clock => mem[0][8].CLK
|
clock => mem[0][8].CLK
|
reset => block_write.ACLR
|
|
reset => wr_ptr[0].ACLR
|
|
reset => wr_ptr[1].ACLR
|
|
reset => wr_ptr[2].ACLR
|
|
reset => wr_ptr[3].ACLR
|
|
reset => wr_ptr[4].ACLR
|
|
reset => wr_ptr[5].ACLR
|
|
reset => mem[63][0].ACLR
|
reset => mem[63][0].ACLR
|
reset => mem[63][1].ACLR
|
reset => mem[63][1].ACLR
|
reset => mem[63][2].ACLR
|
reset => mem[63][2].ACLR
|
reset => mem[63][3].ACLR
|
reset => mem[63][3].ACLR
|
reset => mem[63][4].ACLR
|
reset => mem[63][4].ACLR
|
| Line 170353... |
Line 170883... |
reset => mem[0][4].ACLR
|
reset => mem[0][4].ACLR
|
reset => mem[0][5].ACLR
|
reset => mem[0][5].ACLR
|
reset => mem[0][6].ACLR
|
reset => mem[0][6].ACLR
|
reset => mem[0][7].ACLR
|
reset => mem[0][7].ACLR
|
reset => mem[0][8].ACLR
|
reset => mem[0][8].ACLR
|
reset => block_read.ACLR
|
|
reset => write_tx~reg0.ACLR
|
|
reset => data_out[0]~reg0.ACLR
|
reset => data_out[0]~reg0.ACLR
|
reset => data_out[1]~reg0.ACLR
|
reset => data_out[1]~reg0.ACLR
|
reset => data_out[2]~reg0.ACLR
|
reset => data_out[2]~reg0.ACLR
|
reset => data_out[3]~reg0.ACLR
|
reset => data_out[3]~reg0.ACLR
|
reset => data_out[4]~reg0.ACLR
|
reset => data_out[4]~reg0.ACLR
|
reset => data_out[5]~reg0.ACLR
|
reset => data_out[5]~reg0.ACLR
|
reset => data_out[6]~reg0.ACLR
|
reset => data_out[6]~reg0.ACLR
|
reset => data_out[7]~reg0.ACLR
|
reset => data_out[7]~reg0.ACLR
|
reset => data_out[8]~reg0.ACLR
|
reset => data_out[8]~reg0.ACLR
|
reset => rd_ptr[0].ACLR
|
data_in[0] => mem[0][0].DATAIN
|
reset => rd_ptr[1].ACLR
|
data_in[0] => mem[1][0].DATAIN
|
reset => rd_ptr[2].ACLR
|
data_in[0] => mem[2][0].DATAIN
|
reset => rd_ptr[3].ACLR
|
data_in[0] => mem[3][0].DATAIN
|
reset => rd_ptr[4].ACLR
|
data_in[0] => mem[4][0].DATAIN
|
reset => rd_ptr[5].ACLR
|
data_in[0] => mem[5][0].DATAIN
|
reset => counter[0]~reg0.ACLR
|
data_in[0] => mem[6][0].DATAIN
|
reset => counter[1]~reg0.ACLR
|
data_in[0] => mem[7][0].DATAIN
|
reset => counter[2]~reg0.ACLR
|
data_in[0] => mem[8][0].DATAIN
|
reset => counter[3]~reg0.ACLR
|
data_in[0] => mem[9][0].DATAIN
|
reset => counter[4]~reg0.ACLR
|
data_in[0] => mem[10][0].DATAIN
|
reset => counter[5]~reg0.ACLR
|
data_in[0] => mem[11][0].DATAIN
|
reset => f_empty~reg0.PRESET
|
data_in[0] => mem[12][0].DATAIN
|
reset => f_full~reg0.ACLR
|
data_in[0] => mem[13][0].DATAIN
|
wr_en => always1.IN1
|
data_in[0] => mem[14][0].DATAIN
|
wr_en => block_write.OUTPUTSELECT
|
data_in[0] => mem[15][0].DATAIN
|
wr_en => wr_ptr.OUTPUTSELECT
|
data_in[0] => mem[16][0].DATAIN
|
wr_en => wr_ptr.OUTPUTSELECT
|
data_in[0] => mem[17][0].DATAIN
|
wr_en => wr_ptr.OUTPUTSELECT
|
data_in[0] => mem[18][0].DATAIN
|
wr_en => wr_ptr.OUTPUTSELECT
|
data_in[0] => mem[19][0].DATAIN
|
wr_en => wr_ptr.OUTPUTSELECT
|
data_in[0] => mem[20][0].DATAIN
|
wr_en => wr_ptr.OUTPUTSELECT
|
data_in[0] => mem[21][0].DATAIN
|
rd_en => always1.IN1
|
data_in[0] => mem[22][0].DATAIN
|
rd_en => write_tx.OUTPUTSELECT
|
data_in[0] => mem[23][0].DATAIN
|
rd_en => block_read.OUTPUTSELECT
|
data_in[0] => mem[24][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[25][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[26][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[27][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[28][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[29][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[30][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[31][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[32][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[33][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[34][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[35][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[36][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[37][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[38][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[39][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[40][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[41][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[42][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[43][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[44][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[45][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[46][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[47][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[48][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[49][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[50][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[51][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[52][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[53][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[54][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[55][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[56][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[57][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[58][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[59][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[60][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[61][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[62][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[0] => mem[63][0].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[0][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[1][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[2][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[3][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[4][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[5][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[6][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[7][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[8][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[9][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[10][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[11][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[12][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[13][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[14][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[15][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[16][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[17][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[18][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[19][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[20][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[21][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[22][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[23][1].DATAIN
|
data_in[0] => mem.DATAB
|
data_in[1] => mem[24][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[25][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[26][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[27][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[28][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[29][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[30][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[31][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[32][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[33][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[34][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[35][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[36][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[37][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[38][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[39][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[40][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[41][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[42][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[43][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[44][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[45][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[46][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[47][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[48][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[49][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[50][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[51][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[52][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[53][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[54][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[55][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[56][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[57][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[58][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[59][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[60][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[61][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[62][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[1] => mem[63][1].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[0][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[1][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[2][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[3][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[4][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[5][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[6][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[7][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[8][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[9][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[10][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[11][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[12][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[13][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[14][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[15][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[16][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[17][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[18][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[19][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[20][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[21][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[22][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[23][2].DATAIN
|
data_in[1] => mem.DATAB
|
data_in[2] => mem[24][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[25][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[26][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[27][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[28][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[29][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[30][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[31][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[32][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[33][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[34][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[35][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[36][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[37][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[38][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[39][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[40][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[41][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[42][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[43][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[44][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[45][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[46][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[47][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[48][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[49][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[50][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[51][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[52][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[53][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[54][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[55][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[56][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[57][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[58][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[59][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[60][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[61][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[62][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[2] => mem[63][2].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[0][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[1][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[2][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[3][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[4][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[5][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[6][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[7][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[8][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[9][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[10][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[11][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[12][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[13][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[14][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[15][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[16][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[17][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[18][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[19][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[20][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[21][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[22][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[23][3].DATAIN
|
data_in[2] => mem.DATAB
|
data_in[3] => mem[24][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[25][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[26][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[27][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[28][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[29][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[30][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[31][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[32][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[33][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[34][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[35][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[36][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[37][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[38][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[39][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[40][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[41][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[42][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[43][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[44][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[45][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[46][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[47][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[48][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[49][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[50][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[51][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[52][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[53][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[54][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[55][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[56][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[57][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[58][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[59][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[60][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[61][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[62][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[3] => mem[63][3].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[0][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[1][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[2][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[3][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[4][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[5][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[6][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[7][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[8][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[9][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[10][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[11][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[12][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[13][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[14][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[15][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[16][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[17][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[18][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[19][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[20][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[21][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[22][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[23][4].DATAIN
|
data_in[3] => mem.DATAB
|
data_in[4] => mem[24][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[25][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[26][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[27][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[28][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[29][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[30][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[31][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[32][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[33][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[34][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[35][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[36][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[37][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[38][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[39][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[40][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[41][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[42][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[43][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[44][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[45][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[46][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[47][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[48][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[49][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[50][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[51][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[52][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[53][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[54][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[55][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[56][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[57][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[58][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[59][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[60][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[61][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[62][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[4] => mem[63][4].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[0][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[1][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[2][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[3][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[4][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[5][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[6][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[7][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[8][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[9][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[10][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[11][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[12][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[13][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[14][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[15][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[16][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[17][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[18][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[19][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[20][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[21][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[22][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[23][5].DATAIN
|
data_in[4] => mem.DATAB
|
data_in[5] => mem[24][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[25][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[26][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[27][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[28][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[29][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[30][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[31][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[32][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[33][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[34][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[35][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[36][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[37][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[38][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[39][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[40][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[41][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[42][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[43][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[44][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[45][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[46][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[47][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[48][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[49][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[50][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[51][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[52][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[53][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[54][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[55][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[56][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[57][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[58][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[59][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[60][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[61][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[62][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[5] => mem[63][5].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[0][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[1][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[2][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[3][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[4][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[5][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[6][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[7][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[8][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[9][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[10][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[11][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[12][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[13][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[14][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[15][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[16][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[17][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[18][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[19][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[20][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[21][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[22][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[23][6].DATAIN
|
data_in[5] => mem.DATAB
|
data_in[6] => mem[24][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[25][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[26][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[27][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[28][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[29][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[30][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[31][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[32][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[33][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[34][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[35][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[36][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[37][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[38][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[39][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[40][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[41][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[42][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[43][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[44][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[45][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[46][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[47][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[48][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[49][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[50][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[51][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[52][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[53][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[54][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[55][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[56][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[57][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[58][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[59][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[60][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[61][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[62][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[6] => mem[63][6].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[0][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[1][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[2][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[3][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[4][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[5][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[6][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[7][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[8][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[9][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[10][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[11][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[12][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[13][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[14][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[15][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[16][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[17][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[18][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[19][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[20][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[21][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[22][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[23][7].DATAIN
|
data_in[6] => mem.DATAB
|
data_in[7] => mem[24][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[25][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[26][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[27][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[28][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[29][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[30][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[31][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[32][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[33][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[34][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[35][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[36][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[37][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[38][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[39][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[40][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[41][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[42][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[43][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[44][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[45][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[46][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[47][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[48][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[49][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[50][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[51][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[52][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[53][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[54][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[55][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[56][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[57][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[58][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[59][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[60][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[61][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[62][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[7] => mem[63][7].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[0][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[1][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[2][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[3][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[4][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[5][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[6][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[7][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[8][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[9][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[10][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[11][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[12][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[13][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[14][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[15][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[16][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[17][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[18][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[19][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[20][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[21][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[22][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[23][8].DATAIN
|
data_in[7] => mem.DATAB
|
data_in[8] => mem[24][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[25][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[26][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[27][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[28][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[29][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[30][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[31][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[32][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[33][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[34][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[35][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[36][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[37][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[38][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[39][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[40][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[41][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[42][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[43][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[44][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[45][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[46][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[47][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[48][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[49][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[50][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[51][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[52][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[53][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[54][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[55][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[56][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[57][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[58][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[59][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[60][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[61][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[62][8].DATAIN
|
data_in[8] => mem.DATAB
|
data_in[8] => mem[63][8].DATAIN
|
data_in[8] => mem.DATAB
|
wr_ptr[0] => Decoder0.IN5
|
data_in[8] => mem.DATAB
|
wr_ptr[1] => Decoder0.IN4
|
data_in[8] => mem.DATAB
|
wr_ptr[2] => Decoder0.IN3
|
data_in[8] => mem.DATAB
|
wr_ptr[3] => Decoder0.IN2
|
data_in[8] => mem.DATAB
|
wr_ptr[4] => Decoder0.IN1
|
data_in[8] => mem.DATAB
|
wr_ptr[5] => Decoder0.IN0
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux0.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux1.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux2.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux3.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux4.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux5.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux6.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux7.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[0] => Mux8.IN5
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux0.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux1.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux2.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux3.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux4.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux5.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux6.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux7.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[1] => Mux8.IN4
|
data_in[8] => mem.DATAB
|
rd_ptr[2] => Mux0.IN3
|
f_full <= f_full~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rd_ptr[2] => Mux1.IN3
|
write_tx <= write_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rd_ptr[2] => Mux2.IN3
|
f_empty <= f_empty~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
rd_ptr[2] => Mux3.IN3
|
|
rd_ptr[2] => Mux4.IN3
|
|
rd_ptr[2] => Mux5.IN3
|
|
rd_ptr[2] => Mux6.IN3
|
|
rd_ptr[2] => Mux7.IN3
|
|
rd_ptr[2] => Mux8.IN3
|
|
rd_ptr[3] => Mux0.IN2
|
|
rd_ptr[3] => Mux1.IN2
|
|
rd_ptr[3] => Mux2.IN2
|
|
rd_ptr[3] => Mux3.IN2
|
|
rd_ptr[3] => Mux4.IN2
|
|
rd_ptr[3] => Mux5.IN2
|
|
rd_ptr[3] => Mux6.IN2
|
|
rd_ptr[3] => Mux7.IN2
|
|
rd_ptr[3] => Mux8.IN2
|
|
rd_ptr[4] => Mux0.IN1
|
|
rd_ptr[4] => Mux1.IN1
|
|
rd_ptr[4] => Mux2.IN1
|
|
rd_ptr[4] => Mux3.IN1
|
|
rd_ptr[4] => Mux4.IN1
|
|
rd_ptr[4] => Mux5.IN1
|
|
rd_ptr[4] => Mux6.IN1
|
|
rd_ptr[4] => Mux7.IN1
|
|
rd_ptr[4] => Mux8.IN1
|
|
rd_ptr[5] => Mux0.IN0
|
|
rd_ptr[5] => Mux1.IN0
|
|
rd_ptr[5] => Mux2.IN0
|
|
rd_ptr[5] => Mux3.IN0
|
|
rd_ptr[5] => Mux4.IN0
|
|
rd_ptr[5] => Mux5.IN0
|
|
rd_ptr[5] => Mux6.IN0
|
|
rd_ptr[5] => Mux7.IN0
|
|
rd_ptr[5] => Mux8.IN0
|
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter[4] <= counter[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
counter[5] <= counter[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b
|
|SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b
|
CLK => PB_state.OUTPUTSELECT
|
CLK => PB_state.OUTPUTSELECT
|
CLK => PB_down~reg0.CLK
|
CLK => PB_down~reg0.CLK
|
| Line 171118... |
Line 171672... |
clk_reduced <= clk_reduced_i.DB_MAX_OUTPUT_PORT_TYPE
|
clk_reduced <= clk_reduced_i.DB_MAX_OUTPUT_PORT_TYPE
|
clk_100_reduced <= clk_100_reduced_i.DB_MAX_OUTPUT_PORT_TYPE
|
clk_100_reduced <= clk_100_reduced_i.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|SPW_ULIGHT_FIFO|detector_tokens:m_x
|
|SPW_ULIGHT_FIFO|detector_tokens:m_x
|
rx_din => always0.IN0
|
rx_din => rx_din.IN3
|
rx_din => always3.IN0
|
rx_sin => comb.IN0
|
rx_din => control_bit_found.DATAIN
|
rx_sin => always1.IN0
|
rx_din => bit_c_0.DATAIN
|
rx_resetn => rx_resetn.IN3
|
rx_din => bit_d_0.DATAIN
|
|
rx_din => bit_c_1.DATAIN
|
|
rx_din => bit_d_1.DATAIN
|
|
rx_sin => always0.IN1
|
|
rx_sin => always3.IN1
|
|
rx_resetn => info[0]~reg0.ACLR
|
|
rx_resetn => info[1]~reg0.ACLR
|
|
rx_resetn => info[2]~reg0.ACLR
|
|
rx_resetn => info[3]~reg0.ACLR
|
|
rx_resetn => info[4]~reg0.ACLR
|
|
rx_resetn => info[5]~reg0.ACLR
|
|
rx_resetn => info[6]~reg0.ACLR
|
|
rx_resetn => info[7]~reg0.ACLR
|
|
rx_resetn => info[8]~reg0.ACLR
|
|
rx_resetn => info[9]~reg0.ACLR
|
|
rx_resetn => info[10]~reg0.ACLR
|
|
rx_resetn => info[11]~reg0.ACLR
|
|
rx_resetn => info[12]~reg0.ACLR
|
|
rx_resetn => info[13]~reg0.ACLR
|
|
rx_resetn => last_was_timec.ACLR
|
|
rx_resetn => last_was_data.ACLR
|
|
rx_resetn => last_was_control.ACLR
|
|
rx_resetn => last_is_timec.ACLR
|
|
rx_resetn => last_is_data.ACLR
|
|
rx_resetn => last_is_control.ACLR
|
|
rx_resetn => timecode[0].ACLR
|
|
rx_resetn => timecode[1].ACLR
|
|
rx_resetn => timecode[2].ACLR
|
|
rx_resetn => timecode[3].ACLR
|
|
rx_resetn => timecode[4].ACLR
|
|
rx_resetn => timecode[5].ACLR
|
|
rx_resetn => timecode[6].ACLR
|
|
rx_resetn => timecode[7].ACLR
|
|
rx_resetn => data_l_r[1].ACLR
|
|
rx_resetn => data_l_r[2].ACLR
|
|
rx_resetn => data_l_r[3].ACLR
|
|
rx_resetn => data_l_r[4].ACLR
|
|
rx_resetn => data_l_r[5].ACLR
|
|
rx_resetn => data_l_r[6].ACLR
|
|
rx_resetn => data_l_r[7].ACLR
|
|
rx_resetn => data[0].ACLR
|
|
rx_resetn => data[1].ACLR
|
|
rx_resetn => data[2].ACLR
|
|
rx_resetn => data[3].ACLR
|
|
rx_resetn => data[4].ACLR
|
|
rx_resetn => data[5].ACLR
|
|
rx_resetn => data[6].ACLR
|
|
rx_resetn => data[7].ACLR
|
|
rx_resetn => data[8].ACLR
|
|
rx_resetn => data[9].ACLR
|
|
rx_resetn => control_l_r[0].ACLR
|
|
rx_resetn => control_l_r[1].ACLR
|
|
rx_resetn => control_l_r[2].ACLR
|
|
rx_resetn => control_l_r[3].ACLR
|
|
rx_resetn => control[0].ACLR
|
|
rx_resetn => control[1].ACLR
|
|
rx_resetn => control[2].ACLR
|
|
rx_resetn => control[3].ACLR
|
|
rx_resetn => bit_d_7.ACLR
|
|
rx_resetn => bit_d_5.ACLR
|
|
rx_resetn => bit_d_3.ACLR
|
|
rx_resetn => bit_d_1.ACLR
|
|
rx_resetn => bit_c_3.ACLR
|
|
rx_resetn => bit_c_1.ACLR
|
|
rx_resetn => bit_d_8.ACLR
|
|
rx_resetn => bit_d_6.ACLR
|
|
rx_resetn => bit_d_4.ACLR
|
|
rx_resetn => bit_d_2.ACLR
|
|
rx_resetn => bit_d_0.ACLR
|
|
rx_resetn => bit_c_2.ACLR
|
|
rx_resetn => bit_c_0.ACLR
|
|
rx_resetn => counter_neg[0].PRESET
|
|
rx_resetn => counter_neg[1].ACLR
|
|
rx_resetn => counter_neg[2].ACLR
|
|
rx_resetn => counter_neg[3].ACLR
|
|
rx_resetn => counter_neg[4].ACLR
|
|
rx_resetn => counter_neg[5].ACLR
|
|
rx_resetn => control_bit_found.ACLR
|
|
rx_resetn => is_control.ACLR
|
|
rx_resetn => rx_error.ACLR
|
|
rx_resetn => rx_got_fct.ACLR
|
|
rx_resetn => rx_got_time_code.ACLR
|
|
rx_resetn => rx_got_nchar.ACLR
|
|
rx_resetn => rx_got_null.ACLR
|
|
rx_resetn => ready_data_p_r.ACLR
|
|
rx_resetn => ready_control_p_r.ACLR
|
|
rx_resetn => control_r[0].ACLR
|
|
rx_resetn => control_r[1].ACLR
|
|
rx_resetn => control_r[2].ACLR
|
|
rx_resetn => control_r[3].ACLR
|
|
rx_resetn => control_p_r[0].ACLR
|
|
rx_resetn => control_p_r[1].ACLR
|
|
rx_resetn => control_p_r[2].ACLR
|
|
rx_resetn => control_p_r[3].ACLR
|
|
rx_resetn => dta_timec[0].ACLR
|
|
rx_resetn => dta_timec[1].ACLR
|
|
rx_resetn => dta_timec[2].ACLR
|
|
rx_resetn => dta_timec[3].ACLR
|
|
rx_resetn => dta_timec[4].ACLR
|
|
rx_resetn => dta_timec[5].ACLR
|
|
rx_resetn => dta_timec[6].ACLR
|
|
rx_resetn => dta_timec[7].ACLR
|
|
rx_resetn => dta_timec[8].ACLR
|
|
rx_resetn => dta_timec_p[0].ACLR
|
|
rx_resetn => dta_timec_p[1].ACLR
|
|
rx_resetn => dta_timec_p[2].ACLR
|
|
rx_resetn => dta_timec_p[3].ACLR
|
|
rx_resetn => dta_timec_p[4].ACLR
|
|
rx_resetn => dta_timec_p[5].ACLR
|
|
rx_resetn => dta_timec_p[6].ACLR
|
|
rx_resetn => dta_timec_p[7].ACLR
|
|
rx_resetn => dta_timec_p[8].ACLR
|
|
info[0] <= info[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[0] <= info[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[1] <= info[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[1] <= info[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[2] <= info[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[2] <= info[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[3] <= info[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[3] <= info[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[4] <= info[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[4] <= info[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| Line 171250... |
Line 171692... |
info[11] <= info[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[11] <= info[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[12] <= info[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[12] <= info[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[13] <= info[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
info[13] <= info[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_data:capture_d
|
|
negedge_clk => bit_d_8~reg0.CLK
|
|
negedge_clk => bit_d_6~reg0.CLK
|
|
negedge_clk => bit_d_4~reg0.CLK
|
|
negedge_clk => bit_d_2~reg0.CLK
|
|
negedge_clk => bit_d_0~reg0.CLK
|
|
posedge_clk => bit_d_9~reg0.CLK
|
|
posedge_clk => bit_d_7~reg0.CLK
|
|
posedge_clk => bit_d_5~reg0.CLK
|
|
posedge_clk => bit_d_3~reg0.CLK
|
|
posedge_clk => bit_d_1~reg0.CLK
|
|
rx_resetn => bit_d_8~reg0.ACLR
|
|
rx_resetn => bit_d_6~reg0.ACLR
|
|
rx_resetn => bit_d_4~reg0.ACLR
|
|
rx_resetn => bit_d_2~reg0.ACLR
|
|
rx_resetn => bit_d_0~reg0.ACLR
|
|
rx_resetn => bit_d_9~reg0.ACLR
|
|
rx_resetn => bit_d_7~reg0.ACLR
|
|
rx_resetn => bit_d_5~reg0.ACLR
|
|
rx_resetn => bit_d_3~reg0.ACLR
|
|
rx_resetn => bit_d_1~reg0.ACLR
|
|
rx_din => bit_d_0~reg0.DATAIN
|
|
rx_din => bit_d_1~reg0.DATAIN
|
|
bit_d_0 <= bit_d_0~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_1 <= bit_d_1~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_2 <= bit_d_2~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_3 <= bit_d_3~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_4 <= bit_d_4~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_5 <= bit_d_5~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_6 <= bit_d_6~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_7 <= bit_d_7~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_8 <= bit_d_8~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
bit_d_9 <= bit_d_9~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_control:capture_c
|
|
negedge_clk => bit_c_2~reg0.CLK
|
|
negedge_clk => bit_c_0~reg0.CLK
|
|
posedge_clk => bit_c_3~reg0.CLK
|
|
posedge_clk => bit_c_1~reg0.CLK
|
|
rx_resetn => bit_c_2~reg0.ACLR
|
|
rx_resetn => bit_c_0~reg0.ACLR
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rx_resetn => bit_c_3~reg0.ACLR
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rx_resetn => bit_c_1~reg0.ACLR
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rx_din => bit_c_0~reg0.DATAIN
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rx_din => bit_c_1~reg0.DATAIN
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bit_c_0 <= bit_c_0~reg0.DB_MAX_OUTPUT_PORT_TYPE
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bit_c_1 <= bit_c_1~reg0.DB_MAX_OUTPUT_PORT_TYPE
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bit_c_2 <= bit_c_2~reg0.DB_MAX_OUTPUT_PORT_TYPE
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bit_c_3 <= bit_c_3~reg0.DB_MAX_OUTPUT_PORT_TYPE
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|SPW_ULIGHT_FIFO|detector_tokens:m_x|counter_neg:cnt_neg
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negedge_clk => counter_neg[0]~reg0.CLK
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negedge_clk => counter_neg[1]~reg0.CLK
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negedge_clk => counter_neg[2]~reg0.CLK
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negedge_clk => counter_neg[3]~reg0.CLK
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negedge_clk => counter_neg[4]~reg0.CLK
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negedge_clk => counter_neg[5]~reg0.CLK
|
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negedge_clk => control_bit_found.CLK
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negedge_clk => is_control~reg0.CLK
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rx_resetn => counter_neg[0]~reg0.PRESET
|
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rx_resetn => counter_neg[1]~reg0.ACLR
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rx_resetn => counter_neg[2]~reg0.ACLR
|
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rx_resetn => counter_neg[3]~reg0.ACLR
|
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rx_resetn => counter_neg[4]~reg0.ACLR
|
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rx_resetn => counter_neg[5]~reg0.ACLR
|
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rx_resetn => control_bit_found.ACLR
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rx_resetn => is_control~reg0.ACLR
|
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rx_din => control_bit_found.DATAIN
|
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is_control <= is_control~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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counter_neg[0] <= counter_neg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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counter_neg[1] <= counter_neg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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counter_neg[2] <= counter_neg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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counter_neg[3] <= counter_neg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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counter_neg[4] <= counter_neg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
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counter_neg[5] <= counter_neg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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|
