| Line 50... |
Line 50... |
wire [8:0] top_tx_data;
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wire [8:0] top_tx_data;
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wire [7:0] time_out;
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wire [7:0] time_out;
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wire tick_out;
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wire tick_out;
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wire clk_250_sys;
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|
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assign LED[7:7] = pll_tx_locked_export;
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assign LED[7:7] = pll_tx_locked_export;
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ulight_fifo u0 (
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ulight_fifo u0 (
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.auto_start_external_connection_export (top_auto_start), // auto_start_external_connection.export
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.auto_start_external_connection_export (top_auto_start), // auto_start_external_connection.export
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.clk_clk (FPGA_CLK1_50), // clk.clk
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.clk_clk (FPGA_CLK1_50), // clk.clk
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| Line 85... |
Line 87... |
.memory_mem_odt (<connected-to-memory_mem_odt>), // .mem_odt
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.memory_mem_odt (<connected-to-memory_mem_odt>), // .mem_odt
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.memory_mem_dm (<connected-to-memory_mem_dm>), // .mem_dm
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.memory_mem_dm (<connected-to-memory_mem_dm>), // .mem_dm
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.memory_oct_rzqin (<connected-to-memory_oct_rzqin>), // .oct_rzqin
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.memory_oct_rzqin (<connected-to-memory_oct_rzqin>), // .oct_rzqin
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*/
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*/
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.pll_0_locked_export (pll_tx_locked_export), // pll_0_locked.export
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.pll_0_locked_export (pll_tx_locked_export), // pll_0_locked.export
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.pll_0_outclk0_clk (clk_400_mhz), // pll_0_outclk0.clk
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.pll_0_outclk0_clk (clk_400_mhz),
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//.pll_0_outclk1_clk (clk_250_sys), // pll_0_outclk0.clk
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.reset_reset_n (reset_spw_n_b), // reset.reset_n
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.reset_reset_n (reset_spw_n_b), // reset.reset_n
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.timecode_ready_rx_external_connection_export (tick_out), // timecode_ready_rx_external_connection.export
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.timecode_ready_rx_external_connection_export (tick_out), // timecode_ready_rx_external_connection.export
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.timecode_rx_external_connection_export (time_out), // timecode_rx_external_connection.export
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.timecode_rx_external_connection_export (time_out), // timecode_rx_external_connection.export
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.timecode_tx_data_external_connection_export (top_tx_time), // timecode_tx_data_external_connection.export
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.timecode_tx_data_external_connection_export (top_tx_time), // timecode_tx_data_external_connection.export
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.timecode_tx_enable_external_connection_export (top_tx_tick), // timecode_tx_enable_external_connection.export
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.timecode_tx_enable_external_connection_export (top_tx_tick), // timecode_tx_enable_external_connection.export
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| Line 104... |
Line 107... |
spw_ulight_con_top_x A_SPW_TOP(
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spw_ulight_con_top_x A_SPW_TOP(
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.ppll_100_MHZ(ppll_100_MHZ),
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.ppll_100_MHZ(ppll_100_MHZ),
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.ppllclk(clk_pll_mhz),
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.ppllclk(clk_pll_mhz),
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.reset_spw_n_b(reset_spw_n_b),
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.reset_spw_n_b(reset_spw_n_b),
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//.clk_sys_250_mhz(clk_250_sys),
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.top_sin(sin_a),
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.top_sin(sin_a),
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.top_din(din_a),
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.top_din(din_a),
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.top_auto_start(top_auto_start),
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.top_auto_start(top_auto_start),
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.top_link_start(top_link_start),
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.top_link_start(top_link_start),
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