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module SpwTCR(
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/*
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input CLOCK,
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//=================================================================//
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input RESETn,
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//=
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input LINK_START,
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//= SpwTCR
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input LINK_DISABLE,
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//=
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input AUTOSTART,
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//= Author: Tiago da Costa Rodrigues
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output logic [2:0] CURRENTSTATE,
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//= E-Mail: tiagofee@gmail.com
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output logic [10:0] FLAGS,
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//= Licence: LGPL
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input [8:0] DATA_I,
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//=
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input WR_DATA,
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//= Description: TOP module with submodules connections.
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output logic TX_FULL,
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//=
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output logic [8:0] DATA_O,
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//=
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input RD_DATA,
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//=
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output logic RX_EMPTY,
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//= Version History:
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output logic TICK_OUT,
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//= 0.1: 10/01/2016 - First Version
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output logic [7:0] TIME_OUT,
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//=
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input TICK_IN,
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//=================================================================//
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input [7:0] TIME_IN,
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*/
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input [6:0] TX_CLK_DIV,
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module SPW_TOP(
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input SPILL_ENABLE,
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CLOCK,
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input Din,
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RESETn,
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input Sin,
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LINK_START,
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output logic Dout,
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LINK_DISABLE,
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output logic Sout
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AUTOSTART,
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CURRENTSTATE,
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FLAGS,
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DATA_I,
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WR_DATA,
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TX_FULL,
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DATA_O,
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RD_DATA,
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RX_EMPTY,
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TICK_OUT,
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TIME_OUT,
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TICK_IN,
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TIME_IN,
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TX_CLK_DIV,
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SPILL_ENABLE,
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Din,
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Sin,
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Dout,
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Sout
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);
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);
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//control Interface
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input CLOCK;
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input RESETn;
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input LINK_START;
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input LINK_DISABLE;
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input AUTOSTART;
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output logic [2:0] CURRENTSTATE;
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output logic [10:0] FLAGS;
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input [8:0] DATA_I;
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input WR_DATA;
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output logic TX_FULL;
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output logic [8:0] DATA_O;
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input RD_DATA;
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output logic RX_EMPTY;
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input Din;
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input Sin;
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output logic TICK_OUT;
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output logic [7:0] TIME_OUT;
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output logic Dout;
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output logic Sout;
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input TICK_IN;
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input [7:0] TIME_IN;
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input [6:0] TX_CLK_DIV;
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input SPILL_ENABLE;
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//Wires
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logic resetTx_w;
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logic enableTx_w;
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logic sendNULLs_w;
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logic sendFCTs_w;
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logic sendNChars_w;
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logic sendTimeCodes_w;
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logic startupRate_w;
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logic resetRx_w;
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logic enableRx_w;
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logic gotBit_w;
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logic gotFCT_w;
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logic gotNChar_w;
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logic gotTimeCode_w;
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logic gotNULL_w;
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logic creditError_w;
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logic rxError_w;
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logic gotData_w;
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logic gotEEP_w;
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logic gotEOP_w;
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logic creditErr_w;
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logic creditError_tx_w;
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logic creditError_rx_w;
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logic rx_fifo_empty_w;
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logic rx_fifo_full_w;
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logic rx_fifo_read_w;
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logic rx_fifo_write_w;
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logic tx_fifo_empty_w;
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logic tx_fifo_full_w;
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logic tx_fifo_read_w;
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logic tx_fifo_write_w;
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logic tx_clock_en_w;
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logic clk_rx_w;
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logic enableTimer_w;
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logic after128_w;
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logic after64_w;
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logic sendFctReq_w;
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logic sendFctAck_w;
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logic almost_full_w;
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logic [8:0] rx_fifo_data_i_w;
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logic [8:0] rx_fifo_data_o_w;
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logic [8:0] tx_fifo_data_i_w;
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logic [8:0] tx_fifo_data_o_w;
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logic data_req_w;
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logic data_ack_w;
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//Assignments
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assign TX_FULL = tx_fifo_full_w;
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assign RX_EMPTY = rx_fifo_empty_w;
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//Error handle
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assign FLAGS = {rxError_w, creditError_tx_w, creditError_rx_w, gotTimeCode_w, gotFCT_w, gotData_w, gotEEP_w, gotEOP_w, gotNChar_w, gotNULL_w, gotBit_w};
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assign creditError_w = creditError_tx_w | creditError_rx_w;
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SpwTCR_FSM FSM(
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.CLOCK(CLOCK),
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.RESETn(RESETn),
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.LINK_START(LINK_START),
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.LINK_DISABLE(LINK_DISABLE),
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.AUTOSTART(AUTOSTART),
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.CURRENTSTATE(CURRENTSTATE),
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.after128(after128_w),
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.after64(after64_w),
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.enableTimer(enableTimer_w),
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.resetTx(resetTx_w),
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.enableTx(enableTx_w),
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.sendNULLs(sendNULLs_w),
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.sendFCTs(sendFCTs_w),
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.sendNChars(sendNChars_w),
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.sendTimeCodes(sendTimeCodes_w),
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.startupRate(startupRate_w),
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.resetRx(resetRx_w),
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.enableRx(enableRx_w),
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.gotFCT(gotFCT_w),
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.gotNChar(gotNChar_w),
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.gotTimeCode(gotTimeCode_w),
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.gotNULL(gotNULL_w),
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.creditError(creditError_w),
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.rxError(rxError_w)
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);
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SpwTCR_FSM_TIMER FSM_TIMER(
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.CLOCK(CLOCK),
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.RESETn(RESETn),
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.enableTimer(enableTimer_w),
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.after128(after128_w),
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.after64(after64_w)
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);
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SpwTCR_RX_CLOCK_RECOVER RX_CLOCK_RECOVER(
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.Din(Din),
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.Sin(Sin),
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.clk_rx(clk_rx_w)
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);
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SpwTCR_RX_FIFO RX_FIFO(
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.clk(CLOCK),
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.RESETn(RESETn),
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.data_req(RD_DATA),
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.we(rx_fifo_write_w),
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.data_i(rx_fifo_data_i_w),
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.data_o(DATA_O),
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.full(rx_fifo_full_w),
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.almost_full(almost_full_w),
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.empty(rx_fifo_empty_w)
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);
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SpwTCR_RX RX(
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.Din(Din),
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.Sin(Sin),
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.CLK_RX(clk_rx_w),
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.CLOCK(CLOCK),
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.RESETn(RESETn & resetRx_w),
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.TICK_OUT(TICK_OUT),
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.TIME_OUT(TIME_OUT),
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.RX_DATA(rx_fifo_data_i_w),
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.BUFFER_WRITE(rx_fifo_write_w),
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.BUFFER_READY(!rx_fifo_full_w),
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.almost_full(almost_full_w),
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.enableRx(enableRx_w),
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.gotBit(gotBit_w),
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.gotFCT(gotFCT_w),
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.gotNChar(gotNChar_w),
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.gotTimeCode(gotTimeCode_w),
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.gotNULL(gotNULL_w),
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.gotData(gotData_w),
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.gotEEP(gotEEP_w),
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.gotEOP(gotEOP_w),
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.creditErr(creditError_rx_w),
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.rxError(rxError_w),
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.sendFctReq(sendFctReq_w),
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.sendFctAck(sendFctAck_w)
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);
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SpwTCR_TX_FIFO TX_FIFO(
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.CLOCK(CLOCK),
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.RESETn(RESETn),
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.data_req(data_req_w),
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.we(WR_DATA), .data_i(DATA_I),
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.data_o(tx_fifo_data_o_w),
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.data_ack(data_ack_w),
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.full(tx_fifo_full_w),
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.empty(tx_fifo_empty_w)
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);
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SpwTCR_TX_CLOCK TX_CLOCK (
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.CLOCK(CLOCK),
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.RESETn(RESETn),
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.TX_CLK_DIV(TX_CLK_DIV),
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.startupRate(startupRate_w),
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.CLK_EN(tx_clock_en_w)
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);
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SpwTCR_TX TX(
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.CLOCK(CLOCK),
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.RESETn(RESETn),
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.CLK_EN(tx_clock_en_w),
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.resetTx(RESETn & resetTx_w),
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.enableTx(enableTx_w),
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.sendNULLs(sendNULLs_w),
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.sendFCTs(sendFCTs_w),
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.sendNChars(sendNChars_w),
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.sendTimeCodes(sendTimeCodes_w),
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.creditErr(creditError_tx_w),
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.TICK_IN(TICK_IN),
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.TIME_IN(TIME_IN),
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.sendFctReq(sendFctReq_w),
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.sendFctAck(sendFctAck_w),
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.spillEnable(SPILL_ENABLE),
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.gotFCT(gotFCT_w),
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.data_ack(data_ack_w),
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.data(tx_fifo_data_o_w),
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.data_req(data_req_w),
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.Dout(Dout),
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.Sout(Sout)
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);
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endmodule
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endmodule
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