| Line 52... |
Line 52... |
reg [AWIDTH-1:0] rd_ptr;
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reg [AWIDTH-1:0] rd_ptr;
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reg block_read;
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reg block_read;
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reg block_write;
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reg block_write;
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wire [AWIDTH-1:0] wr;
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wire [AWIDTH-1:0] rd;
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reg [AWIDTH-1:0] credit_counter;
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reg [AWIDTH-1:0] credit_counter;
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//Write pointer
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//Write pointer
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always@(posedge clock or negedge reset)
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always@(posedge clock or negedge reset)
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begin
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begin
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if (!reset)
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if (!reset)
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begin
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begin
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wr_ptr <= {(AWIDTH){1'b0}};
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wr_ptr <= {(AWIDTH){1'b0}};
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mem[0] <= {(DWIDTH){1'b0}};
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mem[1] <= {(DWIDTH){1'b0}};
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mem[2] <= {(DWIDTH){1'b0}};
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mem[3] <= {(DWIDTH){1'b0}};
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mem[4] <= {(DWIDTH){1'b0}};
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mem[5] <= {(DWIDTH){1'b0}};
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mem[6] <= {(DWIDTH){1'b0}};
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mem[7] <= {(DWIDTH){1'b0}};
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mem[8] <= {(DWIDTH){1'b0}};
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mem[9] <= {(DWIDTH){1'b0}};
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mem[10] <= {(DWIDTH){1'b0}};
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mem[11] <= {(DWIDTH){1'b0}};
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mem[12] <= {(DWIDTH){1'b0}};
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mem[13] <= {(DWIDTH){1'b0}};
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mem[14] <= {(DWIDTH){1'b0}};
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mem[15] <= {(DWIDTH){1'b0}};
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mem[16] <= {(DWIDTH){1'b0}};
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mem[17] <= {(DWIDTH){1'b0}};
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mem[18] <= {(DWIDTH){1'b0}};
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mem[19] <= {(DWIDTH){1'b0}};
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mem[20] <= {(DWIDTH){1'b0}};
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mem[21] <= {(DWIDTH){1'b0}};
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mem[22] <= {(DWIDTH){1'b0}};
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mem[23] <= {(DWIDTH){1'b0}};
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mem[24] <= {(DWIDTH){1'b0}};
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mem[25] <= {(DWIDTH){1'b0}};
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mem[26] <= {(DWIDTH){1'b0}};
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mem[27] <= {(DWIDTH){1'b0}};
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mem[28] <= {(DWIDTH){1'b0}};
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mem[29] <= {(DWIDTH){1'b0}};
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mem[30] <= {(DWIDTH){1'b0}};
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mem[31] <= {(DWIDTH){1'b0}};
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mem[32] <= {(DWIDTH){1'b0}};
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mem[33] <= {(DWIDTH){1'b0}};
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mem[34] <= {(DWIDTH){1'b0}};
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mem[35] <= {(DWIDTH){1'b0}};
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mem[36] <= {(DWIDTH){1'b0}};
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mem[37] <= {(DWIDTH){1'b0}};
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mem[38] <= {(DWIDTH){1'b0}};
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mem[39] <= {(DWIDTH){1'b0}};
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mem[40] <= {(DWIDTH){1'b0}};
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mem[41] <= {(DWIDTH){1'b0}};
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mem[42] <= {(DWIDTH){1'b0}};
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mem[43] <= {(DWIDTH){1'b0}};
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mem[44] <= {(DWIDTH){1'b0}};
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mem[45] <= {(DWIDTH){1'b0}};
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mem[46] <= {(DWIDTH){1'b0}};
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mem[47] <= {(DWIDTH){1'b0}};
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mem[48] <= {(DWIDTH){1'b0}};
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mem[49] <= {(DWIDTH){1'b0}};
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mem[50] <= {(DWIDTH){1'b0}};
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mem[51] <= {(DWIDTH){1'b0}};
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mem[52] <= {(DWIDTH){1'b0}};
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mem[53] <= {(DWIDTH){1'b0}};
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mem[54] <= {(DWIDTH){1'b0}};
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mem[55] <= {(DWIDTH){1'b0}};
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mem[56] <= {(DWIDTH){1'b0}};
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mem[57] <= {(DWIDTH){1'b0}};
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mem[58] <= {(DWIDTH){1'b0}};
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mem[59] <= {(DWIDTH){1'b0}};
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mem[60] <= {(DWIDTH){1'b0}};
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mem[61] <= {(DWIDTH){1'b0}};
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mem[62] <= {(DWIDTH){1'b0}};
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mem[63] <= {(DWIDTH){1'b0}};
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block_write <= 1'b0;
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block_write <= 1'b0;
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overflow_credit_error<=1'b0;
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overflow_credit_error<=1'b0;
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end
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end
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else
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else
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begin
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begin
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if(block_write)
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if(block_write)
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begin
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begin
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if(!wr_en)
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if(!wr_en)
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begin
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block_write <= 1'b0;
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block_write <= 1'b0;
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wr_ptr <= wr_ptr + 6'd1;
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end
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//mem[wr_ptr-6'd1]<=data_in;
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end
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end
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else if (wr_en && !f_full)
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else if (wr_en && !f_full)
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begin
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begin
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block_write <= 1'b1;
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block_write <= 1'b1;
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mem[wr_ptr]<=data_in;
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mem[wr_ptr]<=data_in;
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wr_ptr <= wr;
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end
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end
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if(wr_en && credit_counter > 6'd55)
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if(wr_en && credit_counter > 6'd55)
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begin
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begin
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| Line 102... |
Line 173... |
credit_counter <= 6'd55;
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credit_counter <= 6'd55;
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end
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end
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else
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else
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begin
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begin
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if (wr_en && !f_full && !block_write)
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if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))
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begin
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if(rd_en && !f_empty && !block_read)
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begin
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begin
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counter <= counter;
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if(rd_ptr == 6'd8 || rd_ptr == 6'd16 || rd_ptr == 6'd24 || rd_ptr == 6'd32 || rd_ptr == 6'd40 || rd_ptr == 6'd48 || rd_ptr == 6'd56 || rd_ptr == 6'd63)
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end
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credit_counter <= credit_counter - 6'd1 + 6'd8;
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else
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else
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begin
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credit_counter <= credit_counter - 6'd1;
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counter <= counter + 6'd1;
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end
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end
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else if (wr_en && !f_full && !block_write)
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begin
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credit_counter <= credit_counter - 6'd1;
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credit_counter <= credit_counter - 6'd1;
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end
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end
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else if(rd_en && !f_empty && !block_read)
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else if(rd_en && !f_empty && !block_read)
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begin
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begin
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if(rd_ptr == 6'd8 || rd_ptr == 6'd16 || rd_ptr == 6'd24 || rd_ptr == 6'd32 || rd_ptr == 6'd40 || rd_ptr == 6'd48 || rd_ptr == 6'd56 || rd_ptr == 6'd63)
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if(rd_ptr == 6'd8 || rd_ptr == 6'd16 || rd_ptr == 6'd24 || rd_ptr == 6'd32 || rd_ptr == 6'd40 || rd_ptr == 6'd48 || rd_ptr == 6'd56 || rd_ptr == 6'd63)
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begin
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credit_counter <= credit_counter + 6'd8;
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credit_counter <= credit_counter + 6'd8;
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end
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end
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else
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credit_counter <= credit_counter;
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if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))
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begin
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counter <= counter;
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end
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else if (wr_en && !f_full && !block_write)
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begin
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counter <= counter + 6'd1;
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end
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else if(rd_en && !f_empty && !block_read)
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begin
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counter <= counter - 6'd1;
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counter <= counter - 6'd1;
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end
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end
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else
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begin
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counter <= counter;
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end
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if(counter == 6'd63)
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if(counter == 6'd63)
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begin
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begin
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f_full <= 1'b1;
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f_full <= 1'b1;
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end
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end
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| Line 144... |
Line 228... |
end
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end
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else
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else
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begin
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begin
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f_empty <= 1'b0;
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f_empty <= 1'b0;
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end
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end
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end
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end
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end
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end
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//Read pointer
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//Read pointer
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always@(posedge clock or negedge reset)
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always@(posedge clock or negedge reset)
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| Line 170... |
Line 253... |
else
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else
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begin
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begin
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open_slot_fct<= 1'b0;
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open_slot_fct<= 1'b0;
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end
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end
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if(block_read == 1)
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if(block_read)
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begin
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begin
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if(!rd_en)
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if(!rd_en)
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begin
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block_read<= 1'b0;
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block_read<= 1'b0;
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end
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data_out <= mem[rd_ptr];
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end
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end
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else
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else
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if(rd_en && !f_empty)
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if(rd_en && !f_empty)
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begin
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begin
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rd_ptr <= rd;
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block_read<= 1'b1;
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block_read<= 1'b1;
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rd_ptr <= rd_ptr+ 6'd1;
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end
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end
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else
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begin
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data_out <= mem[rd_ptr];
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data_out <= mem[rd_ptr];
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end
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end
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end
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end
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end
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//assign f_empty = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;
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//assign f_empty = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;
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assign wr = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
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//assign wr = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
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assign rd = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
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//assign rd = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
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endmodule
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endmodule
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