| Line 49... |
Line 49... |
reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
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reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
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reg [AWIDTH-1:0] wr_ptr;
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reg [AWIDTH-1:0] wr_ptr;
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reg [AWIDTH-1:0] rd_ptr;
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reg [AWIDTH-1:0] rd_ptr;
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reg block_read;
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reg block_write;
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reg [AWIDTH-1:0] credit_counter;
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reg [AWIDTH-1:0] credit_counter;
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reg [1:0] state_data_write;
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reg [1:0] next_state_data_write;
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reg [1:0] state_data_read;
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reg [1:0] next_state_data_read;
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/****************************************/
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always@(*)
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begin
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next_state_data_write = state_data_write;
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case(state_data_write)
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2'd0:
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begin
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if(wr_en && !f_full)
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begin
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next_state_data_write = 2'd1;
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end
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else
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begin
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next_state_data_write = 2'd0;
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end
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end
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2'd1:
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begin
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if(wr_en)
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begin
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next_state_data_write = 2'd1;
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end
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else
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begin
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next_state_data_write = 2'd2;
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end
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end
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2'd2:
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begin
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next_state_data_write = 2'd0;
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end
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default:
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begin
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next_state_data_write = 2'd0;
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end
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endcase
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end
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/****************************************/
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always@(*)
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begin
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next_state_data_read = state_data_read;
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case(state_data_read)
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2'd0:
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begin
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if(rd_en && !f_empty)
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begin
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next_state_data_read = 2'd1;
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end
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else
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begin
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next_state_data_read = 2'd0;
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end
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end
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2'd1:
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begin
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if(rd_en)
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begin
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next_state_data_read = 2'd1;
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end
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else
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begin
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next_state_data_read = 2'd2;
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end
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end
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2'd2:
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begin
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next_state_data_read = 2'd0;
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end
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default:
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begin
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next_state_data_read = 2'd0;
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end
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endcase
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end
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//Write pointer
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//Write pointer
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always@(posedge clock or negedge reset)
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always@(posedge clock or negedge reset)
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begin
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begin
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if (!reset)
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if (!reset)
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begin
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begin
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| Line 130... |
Line 215... |
mem[59] <= {(DWIDTH){1'b0}};
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mem[59] <= {(DWIDTH){1'b0}};
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mem[60] <= {(DWIDTH){1'b0}};
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mem[60] <= {(DWIDTH){1'b0}};
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mem[61] <= {(DWIDTH){1'b0}};
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mem[61] <= {(DWIDTH){1'b0}};
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mem[62] <= {(DWIDTH){1'b0}};
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mem[62] <= {(DWIDTH){1'b0}};
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mem[63] <= {(DWIDTH){1'b0}};
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mem[63] <= {(DWIDTH){1'b0}};
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block_write <= 1'b0;
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overflow_credit_error<=1'b0;
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overflow_credit_error<=1'b0;
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state_data_write <= 2'd0;
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end
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end
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else
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else
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begin
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begin
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if(block_write)
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state_data_write <= next_state_data_write;
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case(state_data_write)
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2'd0:
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begin
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mem[wr_ptr]<=data_in;
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end
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2'd1:
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begin
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begin
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if(!wr_en)
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mem[wr_ptr]<=mem[wr_ptr];
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end
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2'd2:
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begin
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begin
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block_write <= 1'b0;
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wr_ptr <= wr_ptr + 6'd1;
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wr_ptr <= wr_ptr + 6'd1;
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end
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end
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end
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default:
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else if (wr_en && !f_full)
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begin
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begin
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block_write <= 1'b1;
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mem[wr_ptr]<=mem[wr_ptr];
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mem[wr_ptr]<=data_in;
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wr_ptr <= wr_ptr;
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end
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end
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endcase
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if(wr_en && credit_counter > 6'd55)
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if(wr_en && credit_counter > 6'd55)
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begin
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begin
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overflow_credit_error<=1'b1;
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overflow_credit_error<=1'b1;
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end
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end
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else
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overflow_credit_error <= overflow_credit_error;
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end
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end
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end
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end
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//FULL - EMPTY COUNTER
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//FULL - EMPTY COUNTER
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| Line 171... |
Line 267... |
credit_counter <= 6'd55;
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credit_counter <= 6'd55;
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end
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end
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else
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else
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begin
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begin
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if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))
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if (state_data_write == 2'd2)
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begin
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if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
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credit_counter <= credit_counter - 6'd1 + 6'd8;
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else
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credit_counter <= credit_counter - 6'd1;
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end
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else if (wr_en && !f_full && !block_write)
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begin
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begin
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credit_counter <= credit_counter - 6'd1;
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credit_counter <= credit_counter - 6'd1;
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end
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end
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else if(rd_en && !f_empty && !block_read)
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else if(state_data_read == 2'd2)
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begin
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begin
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if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
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if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
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begin
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begin
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if(credit_counter < 6'd48)
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credit_counter <= credit_counter + 6'd8;
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credit_counter <= credit_counter + 6'd8;
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else
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credit_counter <= credit_counter + 6'd7;
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end
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end
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end
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end
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else
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else
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credit_counter <= credit_counter;
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credit_counter <= credit_counter;
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if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))
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if (state_data_write == 2'd2)
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begin
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begin
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if(counter == 6'd63)
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counter <= counter;
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counter <= counter;
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end
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else
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else if (wr_en && !f_full && !block_write)
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begin
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counter <= counter + 6'd1;
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counter <= counter + 6'd1;
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end
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end
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else if(rd_en && !f_empty && !block_read)
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else if(state_data_read == 2'd2)
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begin
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begin
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if(counter == 6'd0)
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counter <= counter;
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else
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counter <= counter - 6'd1;
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counter <= counter - 6'd1;
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end
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end
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else
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else
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begin
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begin
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counter <= counter;
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counter <= counter;
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| Line 237... |
Line 331... |
if (!reset)
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if (!reset)
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begin
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begin
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rd_ptr <= {(AWIDTH){1'b0}};
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rd_ptr <= {(AWIDTH){1'b0}};
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data_out <= 9'd0;
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data_out <= 9'd0;
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open_slot_fct<= 1'b0;
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open_slot_fct<= 1'b0;
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block_read <= 1'b0;
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state_data_read <= 2'd0;
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end
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end
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else
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else
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begin
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begin
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state_data_read <= next_state_data_read;
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case(state_data_read)
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2'd0:
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begin
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if(rd_en)
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begin
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data_out <= data_out;
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open_slot_fct<= open_slot_fct;
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rd_ptr <= rd_ptr+ 6'd1;
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end
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else
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begin
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open_slot_fct<= open_slot_fct;
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data_out <= mem[rd_ptr];
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end
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end
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2'd1:
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begin
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if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
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if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
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begin
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begin
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open_slot_fct<= 1'b1;
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open_slot_fct<= 1'b1;
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end
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end
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else
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else
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begin
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begin
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open_slot_fct<= 1'b0;
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open_slot_fct<= 1'b0;
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end
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end
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if(block_read)
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data_out <= mem[rd_ptr];
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begin
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if(!rd_en)
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begin
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block_read<= 1'b0;
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end
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end
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2'd2:
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begin
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open_slot_fct<= open_slot_fct;
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data_out <= data_out;
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end
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end
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else
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default:
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if(rd_en && !f_empty)
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begin
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begin
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block_read<= 1'b1;
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rd_ptr <= rd_ptr;
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rd_ptr <= rd_ptr+ 6'd1;
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data_out <= data_out;
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end
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end
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endcase
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data_out <= mem[rd_ptr];
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end
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end
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end
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end
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endmodule
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endmodule
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