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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_rx.v] - Diff between revs 38 and 39

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Rev 38	Rev 39
Line 216...	Line 216...
`mem[60] <= {(DWIDTH){1'b0}};`	`mem[60] <= {(DWIDTH){1'b0}};`
`mem[61] <= {(DWIDTH){1'b0}};`	`mem[61] <= {(DWIDTH){1'b0}};`
`mem[62] <= {(DWIDTH){1'b0}};`	`mem[62] <= {(DWIDTH){1'b0}};`
`mem[63] <= {(DWIDTH){1'b0}};`	`mem[63] <= {(DWIDTH){1'b0}};`

`overflow_credit_error<=1'b0;`
`state_data_write <= 2'd0;`	`state_data_write <= 2'd0;`
`end`	`end`
`else`	`else`
`begin`	`begin`

`state_data_write <= next_state_data_write;`	`state_data_write <= next_state_data_write;`

`case(state_data_write)`	`case(state_data_write)`
`2'd0:`	`2'd0:`
`begin`	`begin`
`if(credit_counter > 6'd55)`
`begin`
`overflow_credit_error <= 1'b1;`
`end`
`else`
`overflow_credit_error <= 1'b0;`

`mem[wr_ptr]<=data_in;`	`mem[wr_ptr]<=data_in;`
`end`	`end`
`2'd1:`	`2'd1:`
`begin`	`begin`
`if(wr_en)`	`if(wr_en)`
Line 263...	Line 255...

`always@(posedge clock or negedge reset)`	`always@(posedge clock or negedge reset)`
`begin`	`begin`
`if (!reset)`	`if (!reset)`
`begin`	`begin`
`f_full <= 1'b0;`	`overflow_credit_error<=1'b0;`
`f_empty <= 1'b1;`
`counter <= {(AWIDTH){1'b0}};`	`counter <= {(AWIDTH){1'b0}};`
`credit_counter <= 6'd55;`	`credit_counter <= 6'd55;`
`end`	`end`
`else`	`else`
`begin`	`begin`

`if (state_data_write == 2'd2)`	`if (state_data_write == 2'd2)`
`begin`	`begin`
	`if(credit_counter == 6'd0)`
	`credit_counter <= credit_counter;`
	`else`
`credit_counter <= credit_counter - 6'd1;`	`credit_counter <= credit_counter - 6'd1;`
`end`	`end`
`else if(state_data_read == 2'd2)`	`else if(state_data_read == 2'd2)`
`begin`	`begin`
`if(rd_ptr == 6'd7 \|\| rd_ptr == 6'd15 \|\| rd_ptr == 6'd23 \|\| rd_ptr == 6'd31 \|\| rd_ptr == 6'd39 \|\| rd_ptr == 6'd47 \|\| rd_ptr == 6'd55 \|\| rd_ptr == 6'd63)`	`if(rd_ptr == 6'd7 \|\| rd_ptr == 6'd15 \|\| rd_ptr == 6'd23 \|\| rd_ptr == 6'd31 \|\| rd_ptr == 6'd39 \|\| rd_ptr == 6'd47 \|\| rd_ptr == 6'd55 \|\| rd_ptr == 6'd63)`
Line 284...	Line 278...
`if(credit_counter < 6'd48)`	`if(credit_counter < 6'd48)`
`credit_counter <= credit_counter + 6'd8;`	`credit_counter <= credit_counter + 6'd8;`
`else`	`else`
`credit_counter <= credit_counter + 6'd7;`	`credit_counter <= credit_counter + 6'd7;`
`end`	`end`
`end`
`else`	`else`
`credit_counter <= credit_counter;`	`credit_counter <= credit_counter;`
	`end`
	`else`
	`begin`
	`if(credit_counter > 6'd55)`
	`begin`
	`overflow_credit_error <= 1'b1;`
	`end`
	`else`
	`overflow_credit_error <= 1'b0;`
	`end`

`if (state_data_write == 2'd2)`	`if (state_data_write == 2'd2)`
`begin`	`begin`
`if(counter == 6'd63)`	`if(counter == 6'd63)`
`counter <= counter;`	`counter <= counter;`
Line 306...	Line 309...
`end`	`end`
`else`	`else`
`begin`	`begin`
`counter <= counter;`	`counter <= counter;`
`end`	`end`
	`end`
	`end`

`if(counter == 6'd63)`	`always@(*)`
`begin`	`begin`
`f_full <= 1'b1;`
`end`	`f_full = 1'b0;`
`else`	`f_empty = 1'b0;`

	`if(counter == 6'd63)`
`begin`	`begin`
`f_full <= 1'b0;`	`f_full = 1'b1;`
`end`	`end`

`if(counter == 6'd0)`	`if(counter == 6'd0)`
`begin`	`begin`
`f_empty <= 1'b1;`	`f_empty = 1'b1;`
`end`
`else`
`begin`
`f_empty <= 1'b0;`
`end`
`end`	`end`

`end`	`end`

`//Read pointer`	`//Read pointer`
`always@(posedge clock or negedge reset)`	`always@(posedge clock or negedge reset)`
`begin`	`begin`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_rx.v] - Diff between revs 38 and 39