URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_rx.v] - Diff between revs 39 and 40

Show entire file | Details | Blame | View Log

Rev 39	Rev 40
Line 40...	Line 40...
`input clock, reset, wr_en, rd_en,`	`input clock, reset, wr_en, rd_en,`
`input [DWIDTH-1:0] data_in,`	`input [DWIDTH-1:0] data_in,`
`output reg f_full,f_empty,`	`output reg f_full,f_empty,`
`output reg open_slot_fct,`	`output reg open_slot_fct,`
`output reg overflow_credit_error,`	`output reg overflow_credit_error,`
`output reg [DWIDTH-1:0] data_out,`	`output [DWIDTH-1:0] data_out,`
`output reg [AWIDTH-1:0] counter`	`output reg [AWIDTH-1:0] counter`
`);`	`);`

`reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];`

`reg [AWIDTH-1:0] wr_ptr;`	`reg [AWIDTH-1:0] wr_ptr;`
`reg [AWIDTH-1:0] rd_ptr;`	`reg [AWIDTH-1:0] rd_ptr;`

`reg [AWIDTH-1:0] credit_counter;`	`reg [AWIDTH-1:0] credit_counter;`

Line 57...	Line 55...
`reg [1:0] next_state_data_write;`	`reg [1:0] next_state_data_write;`

`reg [1:0] state_data_read;`	`reg [1:0] state_data_read;`
`reg [1:0] next_state_data_read;`	`reg [1:0] next_state_data_read;`

	`reg [1:0] state_open_slot;`
	`reg [1:0] next_state_open_slot;`

	`reg [10:0] counter_wait;`

	`/****************************************/`

	`always@(*)`
	`begin`
	`next_state_open_slot = state_open_slot;`

	`case(state_open_slot)`
	`2'd0:`
	`begin`
	`if(rd_ptr == 6'd7 \|\| rd_ptr == 6'd15 \|\| rd_ptr == 6'd23 \|\| rd_ptr == 6'd31 \|\| rd_ptr == 6'd39 \|\| rd_ptr == 6'd47 \|\| rd_ptr == 6'd55 \|\| rd_ptr == 6'd63)`
	`begin`
	`next_state_open_slot = 2'd1;`
	`end`
	`else`
	`begin`
	`next_state_open_slot = 2'd0;`
	`end`
	`end`
	`2'd1:`
	`begin`
	`if(counter_wait != 11'd300)`
	`next_state_open_slot = 2'd1;`
	`else`
	`next_state_open_slot = 2'd2;`
	`end`
	`2'd2:`
	`begin`
	`if(rd_ptr == 6'd7 \|\| rd_ptr == 6'd15 \|\| rd_ptr == 6'd23 \|\| rd_ptr == 6'd31 \|\| rd_ptr == 6'd39 \|\| rd_ptr == 6'd47 \|\| rd_ptr == 6'd55 \|\| rd_ptr == 6'd63)`
	`begin`
	`next_state_open_slot = 2'd2;`
	`end`
	`else`
	`begin`
	`next_state_open_slot = 2'd0;`
	`end`

	`end`
	`default:`
	`begin`
	`next_state_open_slot = 2'd0;`
	`end`
	`endcase`
	`end`

`/****************************************/`	`/****************************************/`

`always@(*)`	`always@(*)`
`begin`	`begin`
Line 138...	Line 184...
`next_state_data_read = 2'd0;`	`next_state_data_read = 2'd0;`
`end`	`end`
`endcase`	`endcase`
`end`	`end`

	`always@(posedge clock or negedge reset)`
	`begin`
	`if (!reset)`
	`begin`
	`state_open_slot <= 2'd0;`
	`open_slot_fct<= 1'b0;`
	`counter_wait <= 11'd0;`
	`end`
	`else`
	`begin`
	`state_open_slot <= next_state_open_slot;`

	`case(state_open_slot)`
	`2'd0:`
	`begin`
	`if(rd_ptr == 6'd7 \|\| rd_ptr == 6'd15 \|\| rd_ptr == 6'd23 \|\| rd_ptr == 6'd31 \|\| rd_ptr == 6'd39 \|\| rd_ptr == 6'd47 \|\| rd_ptr == 6'd55 \|\| rd_ptr == 6'd63)`
	`begin`
	`open_slot_fct<= 1'b1;`
	`counter_wait <= counter_wait + 11'd1;`
	`end`
	`else`
	`begin`
	`open_slot_fct<= 1'b0;`
	`end`
	`end`
	`2'd1:`
	`begin`
	`if(counter_wait != 11'd300)`
	`counter_wait <= counter_wait + 11'd1;`
	`else`
	`counter_wait <= counter_wait;`

	`open_slot_fct<= 1'b1;`
	`end`
	`2'd2:`
	`begin`
	`counter_wait <= 11'd0;`
	`open_slot_fct<= 1'b0;`
	`end`
	`default:`
	`begin`
	`open_slot_fct<= open_slot_fct;`
	`end`
	`endcase`

	`end`
	`end`
`//Write pointer`	`//Write pointer`
`always@(posedge clock or negedge reset)`	`always@(posedge clock or negedge reset)`
`begin`	`begin`
`if (!reset)`	`if (!reset)`
`begin`	`begin`
`wr_ptr <= {(AWIDTH){1'b0}};`
`mem[0] <= {(DWIDTH){1'b0}};`
`mem[1] <= {(DWIDTH){1'b0}};`
`mem[2] <= {(DWIDTH){1'b0}};`
`mem[3] <= {(DWIDTH){1'b0}};`
`mem[4] <= {(DWIDTH){1'b0}};`
`mem[5] <= {(DWIDTH){1'b0}};`
`mem[6] <= {(DWIDTH){1'b0}};`
`mem[7] <= {(DWIDTH){1'b0}};`
`mem[8] <= {(DWIDTH){1'b0}};`
`mem[9] <= {(DWIDTH){1'b0}};`
`mem[10] <= {(DWIDTH){1'b0}};`

`mem[11] <= {(DWIDTH){1'b0}};`
`mem[12] <= {(DWIDTH){1'b0}};`
`mem[13] <= {(DWIDTH){1'b0}};`
`mem[14] <= {(DWIDTH){1'b0}};`
`mem[15] <= {(DWIDTH){1'b0}};`
`mem[16] <= {(DWIDTH){1'b0}};`
`mem[17] <= {(DWIDTH){1'b0}};`
`mem[18] <= {(DWIDTH){1'b0}};`
`mem[19] <= {(DWIDTH){1'b0}};`
`mem[20] <= {(DWIDTH){1'b0}};`
`mem[21] <= {(DWIDTH){1'b0}};`

`mem[22] <= {(DWIDTH){1'b0}};`
`mem[23] <= {(DWIDTH){1'b0}};`
`mem[24] <= {(DWIDTH){1'b0}};`
`mem[25] <= {(DWIDTH){1'b0}};`
`mem[26] <= {(DWIDTH){1'b0}};`
`mem[27] <= {(DWIDTH){1'b0}};`
`mem[28] <= {(DWIDTH){1'b0}};`
`mem[29] <= {(DWIDTH){1'b0}};`
`mem[30] <= {(DWIDTH){1'b0}};`
`mem[31] <= {(DWIDTH){1'b0}};`
`mem[32] <= {(DWIDTH){1'b0}};`


`mem[33] <= {(DWIDTH){1'b0}};`
`mem[34] <= {(DWIDTH){1'b0}};`
`mem[35] <= {(DWIDTH){1'b0}};`
`mem[36] <= {(DWIDTH){1'b0}};`
`mem[37] <= {(DWIDTH){1'b0}};`
`mem[38] <= {(DWIDTH){1'b0}};`
`mem[39] <= {(DWIDTH){1'b0}};`
`mem[40] <= {(DWIDTH){1'b0}};`
`mem[41] <= {(DWIDTH){1'b0}};`
`mem[42] <= {(DWIDTH){1'b0}};`
`mem[43] <= {(DWIDTH){1'b0}};`

`mem[44] <= {(DWIDTH){1'b0}};`
`mem[45] <= {(DWIDTH){1'b0}};`
`mem[46] <= {(DWIDTH){1'b0}};`
`mem[47] <= {(DWIDTH){1'b0}};`
`mem[48] <= {(DWIDTH){1'b0}};`
`mem[49] <= {(DWIDTH){1'b0}};`
`mem[50] <= {(DWIDTH){1'b0}};`
`mem[51] <= {(DWIDTH){1'b0}};`
`mem[52] <= {(DWIDTH){1'b0}};`
`mem[53] <= {(DWIDTH){1'b0}};`
`mem[54] <= {(DWIDTH){1'b0}};`

`mem[55] <= {(DWIDTH){1'b0}};`
`mem[56] <= {(DWIDTH){1'b0}};`
`mem[57] <= {(DWIDTH){1'b0}};`
`mem[58] <= {(DWIDTH){1'b0}};`
`mem[59] <= {(DWIDTH){1'b0}};`
`mem[60] <= {(DWIDTH){1'b0}};`
`mem[61] <= {(DWIDTH){1'b0}};`
`mem[62] <= {(DWIDTH){1'b0}};`
`mem[63] <= {(DWIDTH){1'b0}};`

`state_data_write <= 2'd0;`	`state_data_write <= 2'd0;`
	`wr_ptr <= {(AWIDTH){1'b0}};`
`end`	`end`
`else`	`else`
`begin`	`begin`

`state_data_write <= next_state_data_write;`	`state_data_write <= next_state_data_write;`

`case(state_data_write)`	`case(state_data_write)`
`2'd0:`	`2'd0:`
`begin`	`begin`
`mem[wr_ptr]<=data_in;`	`wr_ptr <= wr_ptr;`
`end`	`end`
`2'd1:`	`2'd1:`
`begin`	`begin`
`if(wr_en)`	`wr_ptr <= wr_ptr;`
`mem[wr_ptr]<=data_in;`
`else`
`mem[wr_ptr]<=mem[wr_ptr];`
`end`	`end`
`2'd2:`	`2'd2:`
`begin`	`begin`
`wr_ptr <= wr_ptr + 6'd1;`	`wr_ptr <= wr_ptr + 6'd1;`
`end`	`end`
`default:`	`default:`
`begin`	`begin`
`mem[wr_ptr]<=mem[wr_ptr];`
`wr_ptr <= wr_ptr;`	`wr_ptr <= wr_ptr;`
`end`	`end`
`endcase`	`endcase`

`end`	`end`
Line 253...	Line 270...

`//FULL - EMPTY COUNTER`	`//FULL - EMPTY COUNTER`

`always@(posedge clock or negedge reset)`	`always@(posedge clock or negedge reset)`
`begin`	`begin`

`if (!reset)`	`if (!reset)`
`begin`	`begin`
	`f_full <= 1'b0;`
	`f_empty <= 1'b0;`
`overflow_credit_error<=1'b0;`	`overflow_credit_error<=1'b0;`
`counter <= {(AWIDTH){1'b0}};`	`counter <= {(AWIDTH){1'b0}};`
`credit_counter <= 6'd55;`
`end`	`end`
`else`	`else`
`begin`	`begin`

`if (state_data_write == 2'd2)`	`if (state_data_write == 2'd2)`
`begin`	`begin`
`if(credit_counter == 6'd0)`	`counter <= counter + 6'd1;`
`credit_counter <= credit_counter;`
`else`
`credit_counter <= credit_counter - 6'd1;`
`end`	`end`
`else if(state_data_read == 2'd2)`
`begin`
`if(rd_ptr == 6'd7 \|\| rd_ptr == 6'd15 \|\| rd_ptr == 6'd23 \|\| rd_ptr == 6'd31 \|\| rd_ptr == 6'd39 \|\| rd_ptr == 6'd47 \|\| rd_ptr == 6'd55 \|\| rd_ptr == 6'd63)`
`begin`
`if(credit_counter < 6'd48)`
`credit_counter <= credit_counter + 6'd8;`
`else`	`else`
`credit_counter <= credit_counter + 6'd7;`	`begin`
`end`	`if(counter > 6'd0 && state_data_read == 2'd2)`
	`counter <= counter - 6'd1;`
`else`	`else`
`credit_counter <= credit_counter;`	`counter <= counter;`
`end`	`end`
`else`
`begin`	`if(counter > 6'd56)`
`if(credit_counter > 6'd55)`
`begin`	`begin`
`overflow_credit_error <= 1'b1;`	`overflow_credit_error <= 1'b1;`
`end`	`end`
`else`	`else`
`overflow_credit_error <= 1'b0;`	`overflow_credit_error <= 1'b0;`
`end`

`if (state_data_write == 2'd2)`	`if(counter == 6'd56)`
`begin`	`begin`
`if(counter == 6'd63)`	`f_full <= 1'b1;`
`counter <= counter;`
`else`
`counter <= counter + 6'd1;`
`end`
`else if(state_data_read == 2'd2)`
`begin`
`if(counter == 6'd0)`
`counter <= counter;`
`else`
`counter <= counter - 6'd1;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`counter <= counter;`	`f_full <= 1'b0;`
`end`
`end`	`end`
`end`

`always@(*)`
`begin`

`f_full = 1'b0;`	`if(counter == 6'd0)`
`f_empty = 1'b0;`

`if(counter == 6'd63)`
`begin`	`begin`
`f_full = 1'b1;`	`f_empty <= 1'b1;`
`end`	`end`
	`else`
`if(counter == 6'd0)`
`begin`	`begin`
`f_empty = 1'b1;`	`f_empty <= 1'b0;`
	`end`
`end`	`end`

`end`	`end`


`//Read pointer`	`//Read pointer`
`always@(posedge clock or negedge reset)`	`always@(posedge clock or negedge reset)`
`begin`	`begin`
`if (!reset)`	`if (!reset)`
`begin`	`begin`
`rd_ptr <= {(AWIDTH){1'b0}};`	`rd_ptr <= {(AWIDTH){1'b0}};`
`data_out <= 9'd0;`
`open_slot_fct<= 1'b0;`
`state_data_read <= 2'd0;`	`state_data_read <= 2'd0;`
`end`	`end`
`else`	`else`
`begin`	`begin`

Line 350...	Line 338...
`case(state_data_read)`	`case(state_data_read)`
`2'd0:`	`2'd0:`
`begin`	`begin`
`if(rd_en)`	`if(rd_en)`
`begin`	`begin`
`data_out <= data_out;`
`open_slot_fct<= open_slot_fct;`
`rd_ptr <= rd_ptr+ 6'd1;`	`rd_ptr <= rd_ptr+ 6'd1;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`open_slot_fct<= open_slot_fct;`	`rd_ptr <= rd_ptr;`
`data_out <= mem[rd_ptr];`
`end`	`end`
`end`	`end`
`2'd1:`	`2'd1:`
`begin`	`begin`
`if(rd_ptr == 6'd7 \|\| rd_ptr == 6'd15 \|\| rd_ptr == 6'd23 \|\| rd_ptr == 6'd31 \|\| rd_ptr == 6'd39 \|\| rd_ptr == 6'd47 \|\| rd_ptr == 6'd55 \|\| rd_ptr == 6'd63)`	`rd_ptr <= rd_ptr;`
`begin`
`open_slot_fct<= 1'b1;`
`end`
`else`
`begin`
`open_slot_fct<= 1'b0;`
`end`

`if(rd_en)`
`begin`
`data_out <= mem[rd_ptr];`
`end`
`else`
`begin`
`data_out <= data_out;`
`end`

`end`	`end`
`2'd2:`	`2'd2:`
`begin`	`begin`
`open_slot_fct<= open_slot_fct;`	`rd_ptr <= rd_ptr;`
`data_out <= data_out;`
`end`	`end`
`default:`	`default:`
`begin`	`begin`
`rd_ptr <= rd_ptr;`	`rd_ptr <= rd_ptr;`
`data_out <= data_out;`
`end`	`end`
`endcase`	`endcase`


`end`	`end`
`end`	`end`


	`mem_data mem_dta_fifo_rx(`

	`.clock(clock),`
	`.reset(reset),`

	`.data_in(data_in),`
	`.wr_ptr(wr_ptr),`
	`.rd_ptr(rd_ptr),`
	`.data_out(data_out)`
	`);`
`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

Browse

Tools

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_rx.v] - Diff between revs 39 and 40