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Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Diff between revs 33 and 34

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Rev 33	Rev 34
Line 50...	Line 50...
`reg [AWIDTH-1:0] rd_ptr;`	`reg [AWIDTH-1:0] rd_ptr;`

`reg block_read;`	`reg block_read;`
`reg block_write;`	`reg block_write;`

`wire [AWIDTH-1:0] wr;`
`wire [AWIDTH-1:0] rd;`

`//Write pointer`	`//Write pointer`
`always@(posedge clock or negedge reset)`	`always@(posedge clock or negedge reset)`
`begin`	`begin`
`if (!reset)`	`if (!reset)`
`begin`	`begin`
	`mem[0] <= {(DWIDTH){1'b0}};`
	`mem[1] <= {(DWIDTH){1'b0}};`
	`mem[2] <= {(DWIDTH){1'b0}};`
	`mem[3] <= {(DWIDTH){1'b0}};`
	`mem[4] <= {(DWIDTH){1'b0}};`
	`mem[5] <= {(DWIDTH){1'b0}};`
	`mem[6] <= {(DWIDTH){1'b0}};`
	`mem[7] <= {(DWIDTH){1'b0}};`
	`mem[8] <= {(DWIDTH){1'b0}};`
	`mem[9] <= {(DWIDTH){1'b0}};`
	`mem[10] <= {(DWIDTH){1'b0}};`

	`mem[11] <= {(DWIDTH){1'b0}};`
	`mem[12] <= {(DWIDTH){1'b0}};`
	`mem[13] <= {(DWIDTH){1'b0}};`
	`mem[14] <= {(DWIDTH){1'b0}};`
	`mem[15] <= {(DWIDTH){1'b0}};`
	`mem[16] <= {(DWIDTH){1'b0}};`
	`mem[17] <= {(DWIDTH){1'b0}};`
	`mem[18] <= {(DWIDTH){1'b0}};`
	`mem[19] <= {(DWIDTH){1'b0}};`
	`mem[20] <= {(DWIDTH){1'b0}};`
	`mem[21] <= {(DWIDTH){1'b0}};`

	`mem[22] <= {(DWIDTH){1'b0}};`
	`mem[23] <= {(DWIDTH){1'b0}};`
	`mem[24] <= {(DWIDTH){1'b0}};`
	`mem[25] <= {(DWIDTH){1'b0}};`
	`mem[26] <= {(DWIDTH){1'b0}};`
	`mem[27] <= {(DWIDTH){1'b0}};`
	`mem[28] <= {(DWIDTH){1'b0}};`
	`mem[29] <= {(DWIDTH){1'b0}};`
	`mem[30] <= {(DWIDTH){1'b0}};`
	`mem[31] <= {(DWIDTH){1'b0}};`
	`mem[32] <= {(DWIDTH){1'b0}};`


	`mem[33] <= {(DWIDTH){1'b0}};`
	`mem[34] <= {(DWIDTH){1'b0}};`
	`mem[35] <= {(DWIDTH){1'b0}};`
	`mem[36] <= {(DWIDTH){1'b0}};`
	`mem[37] <= {(DWIDTH){1'b0}};`
	`mem[38] <= {(DWIDTH){1'b0}};`
	`mem[39] <= {(DWIDTH){1'b0}};`
	`mem[40] <= {(DWIDTH){1'b0}};`
	`mem[41] <= {(DWIDTH){1'b0}};`
	`mem[42] <= {(DWIDTH){1'b0}};`
	`mem[43] <= {(DWIDTH){1'b0}};`

	`mem[44] <= {(DWIDTH){1'b0}};`
	`mem[45] <= {(DWIDTH){1'b0}};`
	`mem[46] <= {(DWIDTH){1'b0}};`
	`mem[47] <= {(DWIDTH){1'b0}};`
	`mem[48] <= {(DWIDTH){1'b0}};`
	`mem[49] <= {(DWIDTH){1'b0}};`
	`mem[50] <= {(DWIDTH){1'b0}};`
	`mem[51] <= {(DWIDTH){1'b0}};`
	`mem[52] <= {(DWIDTH){1'b0}};`
	`mem[53] <= {(DWIDTH){1'b0}};`
	`mem[54] <= {(DWIDTH){1'b0}};`

	`mem[55] <= {(DWIDTH){1'b0}};`
	`mem[56] <= {(DWIDTH){1'b0}};`
	`mem[57] <= {(DWIDTH){1'b0}};`
	`mem[58] <= {(DWIDTH){1'b0}};`
	`mem[59] <= {(DWIDTH){1'b0}};`
	`mem[60] <= {(DWIDTH){1'b0}};`
	`mem[61] <= {(DWIDTH){1'b0}};`
	`mem[62] <= {(DWIDTH){1'b0}};`
	`mem[63] <= {(DWIDTH){1'b0}};`

`wr_ptr <= {(AWIDTH){1'b0}};`	`wr_ptr <= {(AWIDTH){1'b0}};`
`block_write <= 1'b0;`	`block_write <= 1'b0;`
`end`	`end`
`else if(block_write)`	`else`
	`begin`

	`if(block_write)`
`begin`	`begin`
`if(!wr_en)`	`if(!wr_en)`
	`begin`
`block_write <= 1'b0;`	`block_write <= 1'b0;`
	`wr_ptr <= wr_ptr + 6'd1;`
	`end`
`end`	`end`
`else if (wr_en && !f_full)`	`else if (wr_en && !f_full)`
`begin`	`begin`
`block_write <= 1'b1;`	`block_write <= 1'b1;`
`mem[wr_ptr]<=data_in;`	`mem[wr_ptr]<=data_in;`
`wr_ptr <= wr;`	`end`
`end`	`end`
`end`	`end`

`//FULL - EMPTY COUNTER`	`//FULL - EMPTY COUNTER`

Line 87...	Line 162...
`counter <= {(AWIDTH){1'b0}};`	`counter <= {(AWIDTH){1'b0}};`
`end`	`end`
`else`	`else`
`begin`	`begin`

`if (wr_en && !f_full && !block_write)`	`if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))`
`begin`
`if(rd_en && !f_empty && !block_read)`
`begin`	`begin`
`counter <= counter;`	`counter <= counter;`
`end`	`end`
`else`	`else if (wr_en && !f_full && !block_write)`
`begin`	`begin`
`counter <= counter + 6'd1;`	`counter <= counter + 6'd1;`
`end`	`end`
`end`
`else if(rd_en && !f_empty && !block_read)`	`else if(rd_en && !f_empty && !block_read)`
`begin`	`begin`
`counter <= counter - 6'd1;`	`counter <= counter - 6'd1;`
`end`	`end`
	`else`
	`begin`
	`counter <= counter;`
	`end`

`if(counter == 6'd63)`	`if(counter == 6'd63)`
`begin`	`begin`
`f_full <= 1'b1;`	`f_full <= 1'b1;`
`end`	`end`
Line 137...	Line 213...
`block_read <= 1'b0;`	`block_read <= 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`

`if(block_read == 1)`	`if(block_read)`
`begin`	`begin`
`if(!rd_en)`	`if(!rd_en)`
	`begin`
`block_read<= 1'b0;`	`block_read<= 1'b0;`
	`end`
`data_out <= mem[rd_ptr];`
`end`	`end`
`else if(rd_en && !f_empty)`	`else if(rd_en && !f_empty)`
`begin`	`begin`
`rd_ptr <= rd;`
`block_read<= 1'b1;`	`block_read<= 1'b1;`
	`rd_ptr <= rd_ptr+ 6'd1;`

`end`	`end`
`else`
`begin`
`data_out <= mem[rd_ptr];`	`data_out <= mem[rd_ptr];`
`end`

`if(rd_en == 1'b1)`	`if(rd_en)`
`begin`	`begin`
`write_tx<= 1'b0;`	`write_tx<= 1'b0;`
`end`	`end`
`else if(counter > 6'd0)`	`else if(counter > 6'd0)`
`begin`	`begin`
Line 169...	Line 244...

`end`	`end`
`end`	`end`

`//assign f_empty = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;`	`//assign f_empty = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;`
`assign wr = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;`	`//assign wr = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;`
`assign rd = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;`	`//assign rd = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Diff between revs 33 and 34