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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Diff between revs 34 and 36

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Rev 34 Rev 36
Line 50... Line 50...
        reg [AWIDTH-1:0] rd_ptr;
        reg [AWIDTH-1:0] rd_ptr;
 
 
        reg block_read;
        reg block_read;
        reg block_write;
        reg block_write;
 
 
 
 
//Write pointer
//Write pointer
        always@(posedge clock or negedge reset)
        always@(posedge clock or negedge reset)
        begin
        begin
                if (!reset)
                if (!reset)
                begin
                begin
Line 224... Line 223...
                        end
                        end
                        else if(rd_en && !f_empty)
                        else if(rd_en && !f_empty)
                        begin
                        begin
                                block_read<= 1'b1;
                                block_read<= 1'b1;
                                rd_ptr <= rd_ptr+ 6'd1;
                                rd_ptr <= rd_ptr+ 6'd1;
 
 
                        end
                        end
 
 
                        data_out  <= mem[rd_ptr];
                        data_out  <= mem[rd_ptr];
 
 
                        if(rd_en)
                        if(rd_en)
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                                write_tx<= write_tx;
                                write_tx<= write_tx;
 
 
                end
                end
        end
        end
 
 
        //assign f_empty   = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;
 
        //assign wr        = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
 
        //assign rd        = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
 
 
 
endmodule
endmodule
 
 
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