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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Diff between revs 36 and 37

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Rev 36	Rev 37
Line 47...	Line 47...
`reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];`	`reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];`

`reg [AWIDTH-1:0] wr_ptr;`	`reg [AWIDTH-1:0] wr_ptr;`
`reg [AWIDTH-1:0] rd_ptr;`	`reg [AWIDTH-1:0] rd_ptr;`

`reg block_read;`	`reg [1:0] state_data_write;`
`reg block_write;`	`reg [1:0] next_state_data_write;`

	`reg [1:0] state_data_read;`
	`reg [1:0] next_state_data_read;`

	`/****************************************/`

	`always@(*)`
	`begin`
	`next_state_data_write = state_data_write;`

	`case(state_data_write)`
	`2'd0:`
	`begin`
	`if(wr_en && !f_full)`
	`begin`
	`next_state_data_write = 2'd1;`
	`end`
	`else`
	`begin`
	`next_state_data_write = 2'd0;`
	`end`
	`end`
	`2'd1:`
	`begin`
	`if(wr_en)`
	`begin`
	`next_state_data_write = 2'd1;`
	`end`
	`else`
	`begin`
	`next_state_data_write = 2'd2;`
	`end`
	`end`
	`2'd2:`
	`begin`
	`next_state_data_write = 2'd0;`
	`end`
	`default:`
	`begin`
	`next_state_data_write = 2'd0;`
	`end`
	`endcase`
	`end`

	`/****************************************/`

	`always@(*)`
	`begin`
	`next_state_data_read = state_data_read;`

	`case(state_data_read)`
	`2'd0:`
	`begin`
	`if(rd_en && !f_empty)`
	`begin`
	`next_state_data_read = 2'd1;`
	`end`
	`else`
	`begin`
	`next_state_data_read = 2'd0;`
	`end`
	`end`
	`2'd1:`
	`begin`
	`if(rd_en)`
	`begin`
	`next_state_data_read = 2'd1;`
	`end`
	`else`
	`begin`
	`next_state_data_read = 2'd2;`
	`end`
	`end`
	`2'd2:`
	`begin`
	`next_state_data_read = 2'd0;`
	`end`
	`default:`
	`begin`
	`next_state_data_read = 2'd0;`
	`end`
	`endcase`
	`end`

`//Write pointer`	`//Write pointer`
`always@(posedge clock or negedge reset)`	`always@(posedge clock or negedge reset)`
`begin`	`begin`
`if (!reset)`	`if (!reset)`
Line 127...	Line 210...
`mem[61] <= {(DWIDTH){1'b0}};`	`mem[61] <= {(DWIDTH){1'b0}};`
`mem[62] <= {(DWIDTH){1'b0}};`	`mem[62] <= {(DWIDTH){1'b0}};`
`mem[63] <= {(DWIDTH){1'b0}};`	`mem[63] <= {(DWIDTH){1'b0}};`

`wr_ptr <= {(AWIDTH){1'b0}};`	`wr_ptr <= {(AWIDTH){1'b0}};`
`block_write <= 1'b0;`	`state_data_write <= 2'd0;`
`end`	`end`
`else`	`else`
`begin`	`begin`

`if(block_write)`	`state_data_write <= next_state_data_write;`

	`case(state_data_write)`
	`2'd0:`
`begin`	`begin`
`if(!wr_en)`	`mem[wr_ptr]<=data_in;`
	`end`
	`2'd1:`
`begin`	`begin`
`block_write <= 1'b0;`	`mem[wr_ptr]<=mem[wr_ptr];`
`wr_ptr <= wr_ptr + 6'd1;`
`end`	`end`
	`2'd2:`
	`begin`
	`wr_ptr <= wr_ptr + 6'd1;`
`end`	`end`
`else if (wr_en && !f_full)`	`default:`
`begin`	`begin`
`block_write <= 1'b1;`	`mem[wr_ptr]<=mem[wr_ptr];`
`mem[wr_ptr]<=data_in;`	`wr_ptr <= wr_ptr;`
`end`	`end`
	`endcase`
`end`	`end`
`end`	`end`

`//FULL - EMPTY COUNTER`	`//FULL - EMPTY COUNTER`

`always@(posedge clock or negedge reset)`	`always@(posedge clock or negedge reset)`
`begin`	`begin`
`if (!reset)`	`if (!reset)`
`begin`	`begin`
`f_full <= 1'b0;`	`f_full <= 1'b0;`
Line 161...	Line 251...
`counter <= {(AWIDTH){1'b0}};`	`counter <= {(AWIDTH){1'b0}};`
`end`	`end`
`else`	`else`
`begin`	`begin`

`if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))`	`if (state_data_write == 2'd2)`
`begin`	`begin`
	`if(counter == 6'd63)`
`counter <= counter;`	`counter <= counter;`
`end`	`else`
`else if (wr_en && !f_full && !block_write)`
`begin`
`counter <= counter + 6'd1;`	`counter <= counter + 6'd1;`
`end`	`end`
`else if(rd_en && !f_empty && !block_read)`	`else if(state_data_read == 2'd2)`
`begin`	`begin`
	`if(counter == 6'd0)`
	`counter <= counter;`
	`else`
`counter <= counter - 6'd1;`	`counter <= counter - 6'd1;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`counter <= counter;`	`counter <= counter;`
Line 195...	Line 287...
`end`	`end`
`else`	`else`
`begin`	`begin`
`f_empty <= 1'b0;`	`f_empty <= 1'b0;`
`end`	`end`

`end`	`end`
`end`	`end`

`//Read pointer`	`//Read pointer`
`always@(posedge clock or negedge reset)`	`always@(posedge clock or negedge reset)`
Line 207...	Line 298...
`if (!reset)`	`if (!reset)`
`begin`	`begin`
`rd_ptr <= {(AWIDTH){1'b0}};`	`rd_ptr <= {(AWIDTH){1'b0}};`
`data_out <= 9'd0;`	`data_out <= 9'd0;`
`write_tx <= 1'b0;`	`write_tx <= 1'b0;`
`block_read <= 1'b0;`	`state_data_read <= 2'd0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
	`state_data_read <= next_state_data_read;`

`if(block_read)`	`case(state_data_read)`
	`2'd0:`
`begin`	`begin`
`if(!rd_en)`	`if(rd_en)`
`begin`	`begin`
`block_read<= 1'b0;`	`write_tx<= 1'b0;`
`end`	`data_out <= data_out;`
	`rd_ptr <= rd_ptr+ 6'd1;`
`end`	`end`
`else if(rd_en && !f_empty)`	`else`
`begin`	`begin`
`block_read<= 1'b1;`	`data_out <= mem[rd_ptr];`
`rd_ptr <= rd_ptr+ 6'd1;`	`if(counter > 6'd0)`
	`begin`
	`write_tx<= 1'b1;`
`end`	`end`
	`else`
	`write_tx<= 1'b0;`
	`end`
	`end`
	`2'd1:`
	`begin`
	`write_tx<= 1'b0;`
`data_out <= mem[rd_ptr];`	`data_out <= mem[rd_ptr];`
	`end`
`if(rd_en)`	`2'd2:`
`begin`	`begin`
`write_tx<= 1'b0;`	`write_tx<= 1'b0;`
	`data_out <= data_out;`
`end`	`end`
`else if(counter > 6'd0)`	`default:`
`begin`	`begin`
`write_tx<= 1'b1;`	`rd_ptr <= rd_ptr;`
	`data_out <= data_out;`
`end`	`end`
`else`	`endcase`
`write_tx<= write_tx;`

`end`	`end`
`end`	`end`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Diff between revs 36 and 37