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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Diff between revs 37 and 39

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Rev 37	Rev 39
Line 220...	Line 220...
`state_data_write <= next_state_data_write;`	`state_data_write <= next_state_data_write;`

`case(state_data_write)`	`case(state_data_write)`
`2'd0:`	`2'd0:`
`begin`	`begin`
`mem[wr_ptr]<=data_in;`	`mem[wr_ptr]<=mem[wr_ptr];`
	`wr_ptr <= wr_ptr;`
`end`	`end`
`2'd1:`	`2'd1:`
`begin`	`begin`
`mem[wr_ptr]<=mem[wr_ptr];`	`mem[wr_ptr]<=data_in;`
`end`	`end`
`2'd2:`	`2'd2:`
`begin`	`begin`
`wr_ptr <= wr_ptr + 6'd1;`	`wr_ptr <= wr_ptr + 6'd1;`
`end`	`end`
Line 244...	Line 245...
`//FULL - EMPTY COUNTER`	`//FULL - EMPTY COUNTER`
`always@(posedge clock or negedge reset)`	`always@(posedge clock or negedge reset)`
`begin`	`begin`
`if (!reset)`	`if (!reset)`
`begin`	`begin`
`f_full <= 1'b0;`
`f_empty <= 1'b1;`
`counter <= {(AWIDTH){1'b0}};`	`counter <= {(AWIDTH){1'b0}};`
`end`	`end`
`else`	`else`
`begin`	`begin`

Line 270...	Line 269...
`else`	`else`
`begin`	`begin`
`counter <= counter;`	`counter <= counter;`
`end`	`end`

`if(counter == 6'd63)`
`begin`
`f_full <= 1'b1;`
`end`	`end`
`else`
`begin`
`f_full <= 1'b0;`
`end`	`end`

`if(counter == 6'd0)`
	`always@(*)`
`begin`	`begin`
`f_empty <= 1'b1;`
`end`	`f_full = 1'b0;`
`else`	`f_empty = 1'b0;`

	`if(counter == 6'd63)`
`begin`	`begin`
`f_empty <= 1'b0;`	`f_full = 1'b1;`
`end`	`end`

	`if(counter == 6'd0)`
	`begin`
	`f_empty = 1'b1;`
`end`	`end`

`end`	`end`

`//Read pointer`	`//Read pointer`
`always@(posedge clock or negedge reset)`	`always@(posedge clock or negedge reset)`
`begin`	`begin`
Line 310...	Line 311...
`2'd0:`	`2'd0:`
`begin`	`begin`
`if(rd_en)`	`if(rd_en)`
`begin`	`begin`
`write_tx<= 1'b0;`	`write_tx<= 1'b0;`
`data_out <= data_out;`
`rd_ptr <= rd_ptr+ 6'd1;`	`rd_ptr <= rd_ptr+ 6'd1;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`data_out <= mem[rd_ptr];`	`data_out <= mem[rd_ptr];`

`if(counter > 6'd0)`	`if(counter > 6'd0)`
`begin`	`begin`
`write_tx<= 1'b1;`	`write_tx<= 1'b1;`
`end`	`end`
`else`	`else`
Line 332...	Line 333...
`data_out <= mem[rd_ptr];`	`data_out <= mem[rd_ptr];`
`end`	`end`
`2'd2:`	`2'd2:`
`begin`	`begin`
`write_tx<= 1'b0;`	`write_tx<= 1'b0;`
`data_out <= data_out;`	`data_out <= mem[rd_ptr];`
`end`	`end`
`default:`	`default:`
`begin`	`begin`
`rd_ptr <= rd_ptr;`	`rd_ptr <= rd_ptr;`
`data_out <= data_out;`	`data_out <= data_out;`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Diff between revs 37 and 39