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Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fsm_spw.v] - Diff between revs 25 and 33

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Rev 25	Rev 33
Line 48...	Line 48...
`input rx_got_bit,`	`input rx_got_bit,`
`input rx_got_null,`	`input rx_got_null,`
`input rx_got_nchar,`	`input rx_got_nchar,`
`input rx_got_time_code,`	`input rx_got_time_code,`
`input rx_got_fct,`	`input rx_got_fct,`
`output rx_resetn,`	`output reg rx_resetn,`

`//tx status control`	`//tx status control`
`output enable_tx,`	`output reg enable_tx,`
`output send_null_tx,`	`output reg send_null_tx,`
`output send_fct_tx,`	`output reg send_fct_tx,`

`output [5:0] fsm_state`	`output [5:0] fsm_state`

`);`	`);`

Line 73...	Line 73...

`reg [11:0] after128us;`	`reg [11:0] after128us;`
`reg [11:0] after64us;`	`reg [11:0] after64us;`
`reg [11:0] after850ns;`	`reg [11:0] after850ns;`

`//`	`reg got_bit_internal;`
`assign enable_tx = (!resetn \| state_fsm == error_reset \| state_fsm == error_wait)?1'b0:1'b1;`

`//`
`assign rx_resetn = (state_fsm == error_reset)?1'b0:1'b1;`

`//`
`assign send_null_tx = (state_fsm == started \| state_fsm == connecting \| state_fsm == run)?1'b1:1'b0;`

`//`
`assign send_fct_tx = (state_fsm == connecting \| state_fsm == run)?1'b1:1'b0;`

`//`	`//`
`assign fsm_state = state_fsm;`	`assign fsm_state = state_fsm;`

`always@(*)`	`always@(*)`
Line 127...	Line 117...

`if(rx_error \| rx_got_fct \| rx_got_nchar \| rx_got_time_code)`	`if(rx_error \| rx_got_fct \| rx_got_nchar \| rx_got_time_code)`
`begin`	`begin`
`next_state_fsm = error_reset;`	`next_state_fsm = error_reset;`
`end`	`end`
`else if((!link_disable) & (link_start \|(auto_start && rx_got_null)))`	`else if(((!link_disable) & (link_start \|(auto_start & rx_got_null)))==1'b1)`
`begin`	`begin`
`next_state_fsm = started;`	`next_state_fsm = started;`
`end`	`end`

`end`	`end`
Line 140...	Line 130...

`if(rx_error \| rx_got_fct \| rx_got_nchar \| rx_got_time_code \| after128us == 12'd1279)`	`if(rx_error \| rx_got_fct \| rx_got_nchar \| rx_got_time_code \| after128us == 12'd1279)`
`begin`	`begin`
`next_state_fsm = error_reset;`	`next_state_fsm = error_reset;`
`end`	`end`
`else if(rx_got_null & rx_got_bit)`	`else if((rx_got_null & rx_got_bit)== 1'b1)`
`begin`	`begin`
`next_state_fsm = connecting;`	`next_state_fsm = connecting;`
`end`	`end`

`end`	`end`
Line 175...	Line 165...

`end`	`end`
`endcase`	`endcase`
`end`	`end`

`always@(posedge pclk)`	`always@(posedge pclk or negedge resetn)`
`begin`	`begin`
`if(!resetn)`	`if(!resetn)`
`begin`	`begin`
`state_fsm <= error_reset;`	`state_fsm <= error_reset;`

	`rx_resetn <= 1'b0;`

	`enable_tx<= 1'b0;`
	`send_null_tx<= 1'b0;`
	`send_fct_tx<= 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`

`state_fsm <= next_state_fsm;`	`state_fsm <= next_state_fsm;`

`case(state_fsm)`	`case(state_fsm)`
`error_reset:`	`error_reset:`
`begin`	`begin`
	`enable_tx<= 1'b0;`
	`send_null_tx<= 1'b0;`
	`send_fct_tx<= 1'b0;`

	`if(after64us == 12'd639)`
	`rx_resetn <= 1'b1;`
	`else`
	`rx_resetn <= 1'b0;`
`end`	`end`
`error_wait:`	`error_wait:`
`begin`	`begin`
	`rx_resetn <= 1'b1;`
	`enable_tx<= 1'b0;`
	`send_null_tx<= 1'b0;`
	`send_fct_tx<= 1'b0;`
`end`	`end`
`ready:`	`ready:`
`begin`	`begin`
	`rx_resetn <= 1'b1;`
	`enable_tx<= 1'b1;`
	`send_null_tx<= 1'b0;`
	`send_fct_tx<= 1'b0;`
`end`	`end`
`started:`	`started:`
`begin`	`begin`
	`rx_resetn <= 1'b1;`
	`enable_tx<= 1'b1;`
	`send_null_tx<= 1'b1;`
	`send_fct_tx<= 1'b0;`
`end`	`end`
`connecting:`	`connecting:`
`begin`	`begin`
	`rx_resetn <= 1'b1;`
	`enable_tx<= 1'b1;`
	`send_null_tx<= 1'b1;`
	`send_fct_tx<= 1'b1;`
`end`	`end`
`run:`	`run:`
`begin`	`begin`
	`rx_resetn <= 1'b1;`
	`enable_tx<= 1'b1;`
	`send_null_tx<= 1'b1;`
	`send_fct_tx<= 1'b1;`
`end`	`end`
`endcase`	`endcase`

`end`	`end`
`end`	`end`

`always@(posedge pclk)`	`always@(posedge pclk)`
`begin`	`begin`

`if(!resetn)`	`if(!resetn \|\| state_fsm == error_reset)`
`begin`	`begin`
`after128us <= 12'd0;`	`after128us <= 12'd0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
Line 265...	Line 289...

`end`	`end`

`always@(posedge pclk)`	`always@(posedge pclk)`
`begin`	`begin`

`if(!resetn)`	`if(!resetn)`
`begin`	`begin`
`after850ns <= 12'd0;`	`got_bit_internal <= 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`if(state_fsm != run)`	`if(rx_got_bit)`
	`got_bit_internal <= 1'b1;`
	`else`
	`got_bit_internal <= 1'b0;`
	`end`
	`end`

	`always@(posedge pclk)`
	`begin`

	`if(!resetn \| got_bit_internal)`
`begin`	`begin`
`after850ns <= 12'd0;`	`after850ns <= 12'd0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`if(rx_got_bit)`	`if(state_fsm != run)`
`begin`	`begin`
`after850ns <= 12'd0;`	`after850ns <= 12'd0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`if(after850ns < 12'd85 && state_fsm == run)`	`if(after850ns < 12'd85 && state_fsm == run)`
`after850ns <= after850ns + 12'd1;`	`after850ns <= after850ns + 12'd1;`
`else`	`else`
`after850ns <= 12'd0;`	`after850ns <= 12'd0;`
`end`
`end`	`end`
`end`	`end`

`end`	`end`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fsm_spw.v] - Diff between revs 25 and 33