| Line 40... |
Line 40... |
input rx_resetn,
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input rx_resetn,
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output rx_error,
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output rx_error,
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output reg rx_got_bit,
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output reg rx_got_bit,
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output reg rx_got_null,
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output rx_got_null,
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output reg rx_got_nchar,
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output rx_got_nchar,
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output reg rx_got_time_code,
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output rx_got_time_code,
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output reg rx_got_fct,
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output rx_got_fct,
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output reg rx_got_fct_fsm,
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output rx_got_fct_fsm,
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output reg [8:0] rx_data_flag,
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output [8:0] rx_data_flag,
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output reg rx_buffer_write,
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output rx_buffer_write,
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output [7:0] rx_time_out,
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output [7:0] rx_time_out,
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output reg rx_tick_out
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output rx_tick_out
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);
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);
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reg [5:0] counter_neg;
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wire [5:0] counter_neg/* synthesis syn_replicate = 0 */;
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reg control_bit_found;
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reg data_bit_found;
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wire posedge_clk;
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wire posedge_clk;
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wire negedge_clk;
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wire negedge_clk;
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reg [1:0] state_data_process;
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wire bit_c_0;//N
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reg [1:0] next_state_data_process;
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wire bit_c_1;//P
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wire bit_c_2;//N
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wire bit_c_3;//P
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wire bit_d_0;//N
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wire bit_d_1;//P
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wire bit_d_2;//N
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wire bit_d_3;//P
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wire bit_d_4;//N
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wire bit_d_5;//P
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wire bit_d_6;//N
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wire bit_d_7;//P
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wire bit_d_8;//N
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wire bit_d_9;//P
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wire [1:0] state_data_process;
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wire is_control/* synthesis dont_replicate */;
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wire last_is_control;
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wire last_is_data;
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wire last_is_timec;
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reg bit_c_0;//N
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wire [2:0] control_p_r/* synthesis dont_replicate */;
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reg bit_c_1;//P
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wire [7:0] timecode/* synthesis dont_replicate */;
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reg bit_c_2;//N
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reg bit_c_3;//P
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reg bit_d_0;//N
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reg bit_d_1;//P
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reg bit_d_2;//N
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reg bit_d_3;//P
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reg bit_d_4;//N
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reg bit_d_5;//P
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reg bit_d_6;//N
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reg bit_d_7;//P
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reg bit_d_8;//N
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reg bit_d_9;//P
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reg is_control;
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reg parity_received;
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reg last_is_control;
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reg last_is_data;
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reg last_is_timec;
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reg [3:0] control;
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reg [3:0] control_r;
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reg [3:0] control_p_r;
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reg [9:0] data;
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reg [9:0] timecode;
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reg [3:0] control_l_r;
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wire [2:0] control_l_r/* synthesis dont_replicate */;
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reg [9:0] dta_timec;
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wire [8:0] dta_timec_p/* synthesis dont_replicate */;
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reg [9:0] dta_timec_p;
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reg ready_control;
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reg ready_control;
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reg ready_data;
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reg ready_data;
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reg ready_control_p;
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wire ready_control_p_r;
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reg ready_data_p;
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wire ready_data_p_r;
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reg ready_control_p_r;
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wire parity_rec_c;
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reg ready_data_p_r;
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wire parity_rec_d;
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reg parity_rec_c;
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wire parity_rec_c_gen;
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reg parity_rec_d;
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wire parity_rec_d_gen;
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reg rx_error_c;
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wire rx_error_c;
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reg rx_error_d;
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wire rx_error_d;
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reg posedge_p;
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wire posedge_p/* synthesis syn_replicate = 0 */;
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reg f_time;
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//CLOCK RECOVERY
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//CLOCK RECOVERY
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assign posedge_clk = posedge_p;
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assign posedge_clk = posedge_p;
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assign negedge_clk = !posedge_p;
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assign negedge_clk = (f_time)?!posedge_p:1'b0;
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assign rx_time_out = timecode[7:0];
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assign rx_error = rx_error_c | rx_error_d;
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always@(*)
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begin
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rx_got_bit = 1'b0;
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if(rx_din | rx_sin)
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begin
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rx_got_bit = 1'b1;
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end
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end
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always@(*)
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begin
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ready_control = 1'b0;
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ready_data = 1'b0;
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if(counter_neg[5:0] == 6'd4 && !posedge_p)
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begin
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ready_control = 1'b1;
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end
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else if(counter_neg[5:0] == 6'd32 && !posedge_p)
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begin
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ready_data = 1'b1;
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end
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end
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always@(*)
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begin
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ready_control_p = 1'b0;
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ready_data_p = 1'b0;
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if(counter_neg[5:0] == 6'd4 && posedge_p)
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begin
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ready_control_p = 1'b1;
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end
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else if(counter_neg[5:0] == 6'd32 && posedge_p)
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begin
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ready_data_p = 1'b1;
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end
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end
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always@(*)
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begin
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posedge_p = 1'b0;
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if(rx_din ^ rx_sin)
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assign rx_time_out = timecode;
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begin
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posedge_p = 1'b1;
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end
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else
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begin
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posedge_p = 1'b0;
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end
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end
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always@(posedge posedge_clk or negedge rx_resetn)
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begin
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if(!rx_resetn)
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begin
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bit_d_1 <= 1'b0;
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bit_d_3 <= 1'b0;
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bit_d_5 <= 1'b0;
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bit_d_7 <= 1'b0;
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bit_d_9 <= 1'b0;
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end
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else
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begin
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bit_d_1 <= rx_din;
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bit_d_3 <= bit_d_1;
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bit_d_5 <= bit_d_3;
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bit_d_7 <= bit_d_5;
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bit_d_9 <= bit_d_7;
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end
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end
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always@(posedge negedge_clk or negedge rx_resetn)
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begin
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if(!rx_resetn)
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buf (posedge_p,rx_din ^ rx_sin);
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begin
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bit_d_0 <= 1'b0;
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bit_d_2 <= 1'b0;
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bit_d_4 <= 1'b0;
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bit_d_6 <= 1'b0;
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bit_d_8 <= 1'b0;
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end
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else
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begin
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bit_d_0 <= rx_din;
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bit_d_2 <= bit_d_0;
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bit_d_4 <= bit_d_2;
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bit_d_6 <= bit_d_4;
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bit_d_8 <= bit_d_6;
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end
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end
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always@(posedge posedge_clk or negedge rx_resetn)
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always@(posedge posedge_clk or negedge rx_resetn)
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begin
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begin
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if(!rx_resetn)
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if(!rx_resetn)
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begin
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begin
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bit_c_1 <= 1'b0;
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f_time <= 1'b0;
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bit_c_3 <= 1'b0;
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end
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else
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begin
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bit_c_1 <= rx_din;
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bit_c_3 <= bit_c_1;
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end
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end
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always@(posedge negedge_clk or negedge rx_resetn)
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begin
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if(!rx_resetn)
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begin
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bit_c_0 <= 1'b0;
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bit_c_2 <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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bit_c_0 <= rx_din;
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f_time <= 1'b1;
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bit_c_2 <= bit_c_0;
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end
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end
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end
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end
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always@(posedge negedge_clk or negedge rx_resetn)
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always@(*)
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begin
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if(!rx_resetn)
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begin
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rx_got_fct <= 1'b0;
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end
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else
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begin
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if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))
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begin
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rx_got_fct <= 1'b1;
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end
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else
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begin
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rx_got_fct <= 1'b0;
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end
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end
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end
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always@(posedge negedge_clk or negedge rx_resetn)
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begin
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if(!rx_resetn)
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begin
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rx_got_null <= 1'b0;
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rx_got_nchar <= 1'b0;
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rx_got_time_code <= 1'b0;
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end
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else
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begin
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if(last_is_data == 1'b1 )
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begin
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rx_got_nchar <= 1'b1;
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end
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else if(last_is_timec == 1'b1)
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begin
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rx_got_time_code <= 1'b1;
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end
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else if(last_is_control == 1'b1)
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begin
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rx_got_null <= 1'b1;
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end
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else
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begin
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rx_got_null <= 1'b0;
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rx_got_nchar <= 1'b0;
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rx_got_time_code <= 1'b0;
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end
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end
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end
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always@(posedge negedge_clk or negedge rx_resetn)
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begin
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if(!rx_resetn)
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begin
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rx_got_fct_fsm <= 1'b0;
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ready_control_p_r <= 1'b0;
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ready_data_p_r <= 1'b0;
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end
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else
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begin
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if(ready_control || ready_control_p)
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begin
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if(is_control)
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ready_control_p_r <= 1'b1;
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else
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ready_control_p_r <= 1'b0;
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end
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else
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begin
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ready_control_p_r <= 1'b0;
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end
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if(ready_data || ready_data_p)
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begin
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if(!is_control)
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ready_data_p_r <= 1'b1;
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else
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ready_data_p_r <= 1'b0;
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end
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else
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begin
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ready_data_p_r <= 1'b0;
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end
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if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)
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rx_got_fct_fsm <= 1'b1;
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else
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rx_got_fct_fsm <= rx_got_fct_fsm;
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end
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end
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always@(posedge ready_control or negedge rx_resetn )
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begin
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if(!rx_resetn)
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begin
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control_r <= 4'd0;
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parity_rec_c <= 1'b0;
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end
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else
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begin
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control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
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parity_rec_c <= bit_c_3;
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end
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end
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always@(posedge ready_control_p or negedge rx_resetn )
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begin
|
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if(!rx_resetn)
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begin
|
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control_p_r <= 4'd0;
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end
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else
|
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begin
|
begin
|
control_p_r <= control_r;
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end
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end
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rx_got_bit = 1'b0;
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always@(posedge ready_data or negedge rx_resetn )
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if(rx_din | rx_sin)
|
begin
|
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if(!rx_resetn)
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begin
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dta_timec <= 10'd0;
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parity_rec_d <= 1'b0;
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end
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else
|
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begin
|
begin
|
dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
|
rx_got_bit = 1'b1;
|
parity_rec_d <= bit_d_9;
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end
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end
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end
|
end
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always@(posedge ready_data_p or negedge rx_resetn )
|
always@(*)
|
begin
|
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if(!rx_resetn)
|
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begin
|
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dta_timec_p <= 10'd0;
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end
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else
|
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begin
|
|
dta_timec_p <= dta_timec;
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end
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end
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always@(posedge ready_data_p or negedge rx_resetn )
|
|
begin
|
begin
|
|
ready_control = 1'b0;
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ready_data = 1'b0;
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|
|
if(!rx_resetn)
|
if(is_control && counter_neg == 6'd4 && !posedge_p)
|
begin
|
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rx_error_d <= 1'b0;
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|
end
|
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else
|
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begin
|
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if(last_is_control)
|
|
begin
|
begin
|
if(!(dta_timec[8]^control[0]^control[1]) != parity_rec_d)
|
ready_control = 1'b1;
|
begin
|
ready_data = 1'b0;
|
rx_error_d <= 1'b1;
|
|
end
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end
|
end
|
else if(last_is_data)
|
else if(!is_control && counter_neg == 6'd32 && !posedge_p)
|
begin
|
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if(!(dta_timec[8]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_d)
|
|
begin
|
begin
|
rx_error_d <= 1'b1;
|
ready_control = 1'b0;
|
end
|
ready_data = 1'b1;
|
end
|
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end
|
end
|
end
|
end
|
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always@(posedge ready_control_p or negedge rx_resetn )
|
|
begin
|
|
|
|
if(!rx_resetn)
|
rx_buffer_fsm buffer_fsm(
|
begin
|
.posedge_clk(posedge_clk),
|
rx_error_c <= 1'b0;
|
.rx_resetn(rx_resetn),
|
|
|
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.last_is_data(last_is_data),
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.last_is_timec(last_is_timec),
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.last_is_control(last_is_control),
|
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|
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.rx_got_null(rx_got_null),
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.rx_got_nchar(rx_got_nchar),
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.rx_got_time_code(rx_got_time_code)
|
|
);
|
|
|
end
|
rx_data_buffer_data_w buffer_data_flag(
|
else
|
.negedge_clk(negedge_clk),
|
begin
|
.rx_resetn(rx_resetn),
|
if(last_is_control)
|
|
begin
|
.state_data_process(state_data_process),
|
if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)
|
.control(control_p_r),
|
begin
|
.last_is_timec(last_is_timec),
|
rx_error_c <= 1'b1;
|
.last_is_data(last_is_data),
|
end
|
.last_is_control(last_is_control),
|
end
|
|
else if(last_is_data)
|
|
begin
|
|
if(!(control_r[2]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_c)
|
|
begin
|
|
rx_error_c <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
end
|
.rx_buffer_write(rx_buffer_write),
|
|
.rx_tick_out(rx_tick_out)
|
|
|
always@(posedge negedge_clk or negedge rx_resetn)
|
);
|
begin
|
|
|
|
if(!rx_resetn)
|
|
begin
|
|
rx_buffer_write <= 1'b0;
|
|
rx_tick_out <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
|
|
if(!ready_control_p_r && !ready_data_p_r && !ready_control && !ready_data)
|
rx_control_data_rdy control_data_rdy(
|
begin
|
.posedge_clk(posedge_clk),
|
if(last_is_timec == 1'b1)
|
.rx_resetn(rx_resetn),
|
begin
|
|
rx_tick_out <= 1'b1;
|
|
end
|
|
else if(last_is_data == 1'b1)
|
|
begin
|
|
rx_buffer_write <= 1'b1;
|
|
end
|
|
else if(last_is_control == 1'b1)
|
|
begin
|
|
if(control[2:0] == 3'd6)
|
|
begin
|
|
rx_buffer_write <= 1'b1;
|
|
end
|
|
else if(control[2:0] == 3'd5)
|
|
begin
|
|
rx_buffer_write <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
rx_buffer_write <= 1'b0;
|
|
rx_tick_out <= 1'b0;
|
|
end
|
|
end
|
|
end
|
|
|
|
|
.rx_error_c(rx_error_c),
|
|
.rx_error_d(rx_error_d),
|
|
|
always@(posedge negedge_clk or negedge rx_resetn)
|
.control(control_p_r),
|
begin
|
.control_l_r(control_l_r[2:0]),
|
|
|
if(!rx_resetn)
|
.is_control(is_control),
|
begin
|
.counter_neg(counter_neg),
|
is_control <= 1'b0;
|
|
control_bit_found <= 1'b0;
|
|
counter_neg[5:0] <= 6'd1;
|
|
end
|
|
else
|
|
begin
|
|
|
|
control_bit_found <= rx_din;
|
.last_is_control(last_is_control),
|
|
|
case(counter_neg)
|
.rx_error(rx_error),
|
6'd1:
|
.ready_control_p_r(ready_control_p_r),
|
begin
|
.ready_data_p_r(ready_data_p_r),
|
counter_neg[5:0] <= 6'd2;
|
.rx_got_fct_fsm(rx_got_fct_fsm)
|
end
|
);
|
6'd2:
|
|
begin
|
|
if(control_bit_found == 1'b1)
|
|
begin
|
|
is_control <= 1'b1;
|
|
end
|
|
else
|
|
begin
|
|
is_control <= 1'b0;
|
|
end
|
|
|
|
counter_neg[5:0] <= 6'd4;
|
|
end
|
|
6'd4:
|
|
begin
|
|
if(is_control == 1'b1)
|
|
begin
|
|
counter_neg[5:0] <= 6'd2;
|
|
is_control <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
counter_neg[5:0] <= 6'd8;
|
|
end
|
|
end
|
|
6'd8:
|
|
begin
|
|
counter_neg[5:0] <= 6'd16;
|
|
end
|
|
6'd16:
|
|
begin
|
|
counter_neg[5:0] <= 6'd32;
|
|
end
|
|
6'd32:
|
|
begin
|
|
is_control <= 1'b0;
|
|
counter_neg[5:0] <= 6'd2;
|
|
end
|
|
default:
|
|
begin
|
|
is_control <= is_control;
|
|
counter_neg[5:0] <= counter_neg[5:0];
|
|
end
|
|
endcase
|
|
|
|
end
|
|
end
|
|
|
|
always@(*)
|
rx_data_control_p data_control(
|
begin
|
.posedge_clk(posedge_clk),
|
|
.rx_resetn(rx_resetn),
|
|
|
|
.bit_c_3(bit_c_3),
|
|
.bit_c_2(bit_c_2),
|
|
.bit_c_1(bit_c_1),
|
|
.bit_c_0(bit_c_0),
|
|
|
|
.bit_d_9(bit_d_9),
|
|
.bit_d_8(bit_d_8),
|
|
.bit_d_0(bit_d_0),
|
|
.bit_d_1(bit_d_1),
|
|
.bit_d_2(bit_d_2),
|
|
.bit_d_3(bit_d_3),
|
|
.bit_d_4(bit_d_4),
|
|
.bit_d_5(bit_d_5),
|
|
.bit_d_6(bit_d_6),
|
|
.bit_d_7(bit_d_7),
|
|
|
|
.last_is_control(last_is_control),
|
|
.last_is_data(last_is_data),
|
|
|
|
.is_control(is_control),
|
|
.counter_neg(counter_neg),
|
|
|
|
.dta_timec_p(dta_timec_p),
|
|
.parity_rec_d(parity_rec_d),
|
|
.parity_rec_d_gen(parity_rec_d_gen),
|
|
|
|
.control_p_r(control_p_r),
|
|
.control_l_r(control_l_r),
|
|
.parity_rec_c(parity_rec_c),
|
|
.parity_rec_c_gen(parity_rec_c_gen)
|
|
);
|
|
|
next_state_data_process = state_data_process;
|
|
|
|
case(state_data_process)
|
bit_capture_data capture_d(
|
2'd0:
|
.negedge_clk(negedge_clk),
|
begin
|
.posedge_clk(posedge_clk),
|
if(ready_control_p_r || ready_data_p_r)
|
.rx_resetn(rx_resetn),
|
begin
|
|
next_state_data_process = 2'd1;
|
.rx_din(rx_din),
|
end
|
|
else
|
.bit_d_0(bit_d_0),//N
|
begin
|
.bit_d_1(bit_d_1),//P
|
next_state_data_process = 2'd0;
|
.bit_d_2(bit_d_2),//N
|
end
|
.bit_d_3(bit_d_3),//P
|
end
|
.bit_d_4(bit_d_4),//N
|
2'd1:
|
.bit_d_5(bit_d_5),//P
|
begin
|
.bit_d_6(bit_d_6),//N
|
next_state_data_process = 2'd0;
|
.bit_d_7(bit_d_7),//P
|
end
|
.bit_d_8(bit_d_8),//N
|
default:
|
.bit_d_9(bit_d_9)//P
|
begin
|
);
|
next_state_data_process = 2'd0;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
|
bit_capture_control capture_c(
|
|
.negedge_clk(negedge_clk),
|
|
.posedge_clk(posedge_clk),
|
|
.rx_resetn(rx_resetn),
|
|
|
|
.rx_din(rx_din),
|
|
|
|
.bit_c_0(bit_c_0),
|
|
.bit_c_1(bit_c_1),
|
|
.bit_c_2(bit_c_2),
|
|
.bit_c_3(bit_c_3)
|
|
);
|
|
|
always@(posedge negedge_clk or negedge rx_resetn )
|
counter_neg cnt_neg(
|
begin
|
.negedge_clk(negedge_clk),
|
|
.rx_resetn(rx_resetn),
|
|
.rx_din(rx_din),
|
|
.is_control(is_control),
|
|
.counter_neg(counter_neg)
|
|
);
|
|
|
if(!rx_resetn)
|
rx_data_receive rx_dtarcv (
|
begin
|
.posedge_clk(posedge_clk),
|
control_l_r <= 4'd0;
|
.rx_resetn(rx_resetn),
|
control <= 4'd0;
|
|
data <= 10'd0;
|
|
|
|
last_is_control <= 1'b0;
|
|
last_is_data <= 1'b0;
|
|
last_is_timec <= 1'b0;
|
|
|
|
rx_data_flag <= 9'd0;
|
.ready_control_p_r(ready_control_p_r),
|
timecode <= 10'd0;
|
.ready_data_p_r(ready_data_p_r),
|
|
.ready_control(ready_control),
|
|
.ready_data(ready_data),
|
|
|
state_data_process <= 2'd0;
|
.parity_rec_c(parity_rec_c),
|
end
|
.parity_rec_d(parity_rec_d),
|
else
|
|
begin
|
|
|
|
state_data_process <= next_state_data_process;
|
.parity_rec_c_gen(parity_rec_c_gen),
|
|
.parity_rec_d_gen(parity_rec_d_gen),
|
|
|
case(state_data_process)
|
.control_p_r(control_p_r),
|
2'd0:
|
.dta_timec_p(dta_timec_p),
|
begin
|
|
|
|
if(ready_control_p_r)
|
.control_l_r(control_l_r),
|
begin
|
.state_data_process(state_data_process),
|
control <= control_p_r;
|
|
control_l_r <= control;
|
|
|
|
if(control_p_r[2:0] == 3'd6)
|
.last_is_control(last_is_control),
|
begin
|
.last_is_data(last_is_data),
|
rx_data_flag <= 9'd257;
|
.last_is_timec(last_is_timec),
|
end
|
|
else if(control_p_r[2:0] == 3'd5)
|
|
begin
|
|
rx_data_flag <= 9'd256;
|
|
end
|
|
else
|
|
begin
|
|
rx_data_flag <= rx_data_flag;
|
|
end
|
|
|
|
last_is_control <= 1'b1;
|
.rx_error_c(rx_error_c),
|
last_is_data <= 1'b0;
|
.rx_error_d(rx_error_d),
|
last_is_timec <= 1'b0;
|
.rx_got_fct(rx_got_fct),
|
|
|
end
|
.rx_data_flag(rx_data_flag),
|
else if(ready_data_p_r)
|
|
begin
|
|
if(control[2:0] != 3'd7)
|
|
begin
|
|
data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
|
|
rx_data_flag <= {dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
|
|
last_is_control <=1'b0;
|
|
last_is_data <=1'b1;
|
|
last_is_timec <=1'b0;
|
|
end
|
|
else if(control[2:0] == 3'd7)
|
|
begin
|
|
timecode <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
|
|
last_is_control <= 1'b0;
|
|
last_is_data <= 1'b0;
|
|
last_is_timec <= 1'b1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
timecode <= timecode;
|
|
end
|
|
|
|
end
|
.timecode(timecode)
|
2'd1:
|
);
|
begin
|
|
rx_data_flag <= rx_data_flag;
|
|
timecode <= timecode;
|
|
end
|
|
default:
|
|
begin
|
|
rx_data_flag <= rx_data_flag;
|
|
timecode <= timecode;
|
|
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
