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https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
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| Rev 38 |
Rev 39 |
| Line 405... |
Line 405... |
begin
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begin
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dta_timec_p <= dta_timec;
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dta_timec_p <= dta_timec;
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end
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end
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end
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end
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always@(*)
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always@(posedge ready_data_p or negedge rx_resetn )
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begin
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begin
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rx_error_d = 1'b0;
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if(!rx_resetn)
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begin
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if(last_is_control && ready_data_p)
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rx_error_d <= 1'b0;
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end
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else
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begin
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if(last_is_control)
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begin
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begin
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if(!(dta_timec[8]^control[0]^control[1]) != parity_rec_d)
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if(!(dta_timec[8]^control[0]^control[1]) != parity_rec_d)
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begin
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begin
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rx_error_d = 1'b1;
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rx_error_d <= 1'b1;
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end
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end
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end
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end
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else if(last_is_data && ready_data_p)
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else if(last_is_data)
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begin
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begin
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if(!(dta_timec[8]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_d)
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if(!(dta_timec[8]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_d)
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begin
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begin
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rx_error_d = 1'b1;
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rx_error_d <= 1'b1;
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end
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end
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end
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end
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end
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end
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end
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always@(*)
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always@(posedge ready_control_p or negedge rx_resetn )
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begin
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begin
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rx_error_c = 1'b0;
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if(last_is_control && ready_control_p)
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if(!rx_resetn)
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begin
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rx_error_c <= 1'b0;
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end
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else
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begin
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if(last_is_control)
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begin
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begin
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if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)
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if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)
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begin
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begin
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rx_error_c = 1'b1;
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rx_error_c <= 1'b1;
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end
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end
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end
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end
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else if(last_is_data && ready_control_p)
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else if(last_is_data)
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begin
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begin
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if(!(control_r[2]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_c)
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if(!(control_r[2]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_c)
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begin
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begin
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rx_error_c = 1'b1;
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rx_error_c <= 1'b1;
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end
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end
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end
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end
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end
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end
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end
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always@(posedge negedge_clk or negedge rx_resetn)
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always@(posedge negedge_clk or negedge rx_resetn)
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begin
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begin
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if(!rx_resetn)
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if(!rx_resetn)
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begin
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begin
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