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[/] [spacewiresystemc/] [trunk/] [systemC/] [main.cc] - Diff between revs 29 and 40

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Line 1... Line 1...
//+FHDR------------------------------------------------------------------------
 
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
 
//GLADIC Open Source RTL
 
//-----------------------------------------------------------------------------
 
//FILE NAME      :
 
//DEPARTMENT     : IC Design / Verification
 
//AUTHOR         : Felipe Fernandes da Costa
 
//AUTHOR’S EMAIL :
 
//-----------------------------------------------------------------------------
 
//RELEASE HISTORY
 
//VERSION DATE AUTHOR DESCRIPTION
 
//1.0 YYYY-MM-DD name
 
//-----------------------------------------------------------------------------
 
//KEYWORDS : General file searching keywords, leave blank if none.
 
//-----------------------------------------------------------------------------
 
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
 
//-----------------------------------------------------------------------------
 
//PARAMETERS
 
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
 
//e.g.DATA_WIDTH        [32,16] : width of the DATA : 32:
 
//-----------------------------------------------------------------------------
 
//REUSE ISSUES
 
//Reset Strategy        :
 
//Clock Domains         :
 
//Critical Timing       :
 
//Test Features         :
 
//Asynchronous I/F      :
 
//Scan Methodology      :
 
//Instantiations        :
 
//Synthesizable (y/n)   :
 
//Other                 :
 
//-FHDR------------------------------------------------------------------------
 
#include <systemc.h>
#include <systemc.h>
#include <stdio.h>
#include <stdio.h>
#include <vector>
#include <vector>
#include <string>
#include <string>
#include <stdlib.h> 
#include <stdlib.h> 
Line 44... Line 12...
using namespace boost;
using namespace boost;
 
 
#include "../gladicapi/data_recorder.h"
#include "../gladicapi/data_recorder.h"
#include "../gladicapi/data_check.h"
#include "../gladicapi/data_check.h"
 
 
bool enable_null;
 
bool enable_fct;
 
bool enable_time_code;
 
bool enable_n_char;
 
 
 
bool EEP_EOP;
bool EEP_EOP;
 
 
unsigned int finish = 0;
unsigned int finish = 0;
bool link_start = false;
bool link_start = false;
bool link_disable = false;
bool link_disable = false;
Line 98... Line 61...
 
 
unsigned int data_iteration = 0;
unsigned int data_iteration = 0;
unsigned int data_iteration_vlog = 0;
unsigned int data_iteration_vlog = 0;
sc_uint<9> intermediate_data;
sc_uint<9> intermediate_data;
 
 
 
 
 
void data_rx_sc_o(unsigned int type_char, sc_uint<4> control, sc_uint<4> last_control_sys , sc_uint<10> data , sc_uint<10> timecode_sys);
 
 
#include "top_spw.h"
#include "top_spw.h"
 
 
//Data generation
//Data generation
unsigned long int max_data = 100;
unsigned long int max_data = 255;
 
 
std::random_device rd;
std::random_device rd;
std::uniform_int_distribution<unsigned long int> data_in(0,255);
std::uniform_int_distribution<unsigned long int> data_in(0,255);
std::uniform_int_distribution<unsigned long int> nchar(1,max_data-1);//eop-eep
std::uniform_int_distribution<unsigned long int> nchar(1,max_data);//eop-eep
 
 
class sc_TOP_SPW;
class sc_TOP_SPW;
 
 
SC_MODULE(sc_TOP_SPW)
SC_MODULE(sc_TOP_SPW)
{
{
Line 122... Line 88...
        sc_signal<sc_uint<4> > FSM_SPW_OUT;
        sc_signal<sc_uint<4> > FSM_SPW_OUT;
        sc_signal<sc_uint<4> > FSM_TX;
        sc_signal<sc_uint<4> > FSM_TX;
 
 
        sc_signal<sc_uint<10> > CLOCK_GEN;
        sc_signal<sc_uint<10> > CLOCK_GEN;
        sc_signal<bool> E_SEND_DATA;
        sc_signal<bool> E_SEND_DATA;
        //sc_signal<bool> TICKIN_TX;
 
        //sc_signal<sc_uint<8> > TIMEIN_CONTROL_FLAG_TX;
 
 
 
        //sc_signal<bool> TXWRITE_TX;
 
        //sc_signal<sc_uint<9> > TXDATA_FLAGCTRL_TX;
 
 
 
        //sc_signal<bool> READY_TX;
 
        //sc_signal<bool> READY_TICK;
 
 
 
        sc_signal<bool> BUFFER_READY;
        sc_signal<bool> BUFFER_READY;
        sc_signal<sc_uint<9> > DATARX_FLAG;
        sc_signal<sc_uint<9> > DATARX_FLAG;
        sc_signal<bool> BUFFER_WRITE;
        sc_signal<bool> BUFFER_WRITE;
 
 
Line 154... Line 113...
                           LINK_START("LINK_START"),
                           LINK_START("LINK_START"),
                           AUTO_START("AUTO_START"),
                           AUTO_START("AUTO_START"),
                           FSM_SPW_OUT("FSM_SPW_OUT"),
                           FSM_SPW_OUT("FSM_SPW_OUT"),
                           CLOCK_GEN("CLOCK_GEN"),
                           CLOCK_GEN("CLOCK_GEN"),
                           E_SEND_DATA("E_SEND_DATA"),
                           E_SEND_DATA("E_SEND_DATA"),
                           //TICKIN_TX("TICKIN_TX"),
 
                           //TIMEIN_CONTROL_FLAG_TX("TIMEIN_CONTROL_FLAG_TX"),
 
                           //TXWRITE_TX("TXWRITE_TX"),
 
                           //TXDATA_FLAGCTRL_TX("TXDATA_FLAGCTRL_TX"),
 
 
 
                           //READY_TX("READY_TX"),
 
                          //READY_TICK("READY_TICK"),
 
                           DOUT("DOUT"),
                           DOUT("DOUT"),
                           SOUT("SOUT"),
                           SOUT("SOUT"),
 
 
                           FSM_TX("FSM_TX"),
                           FSM_TX("FSM_TX"),
                           DIN("DIN"),
                           DIN("DIN"),
Line 184... Line 136...
        DUT.AUTO_START(AUTO_START);
        DUT.AUTO_START(AUTO_START);
        DUT.LINK_START(LINK_START);
        DUT.LINK_START(LINK_START);
        DUT.FSM_SPW_OUT(FSM_SPW_OUT);
        DUT.FSM_SPW_OUT(FSM_SPW_OUT);
        DUT.CLOCK_GEN(CLOCK_GEN);
        DUT.CLOCK_GEN(CLOCK_GEN);
        DUT.E_SEND_DATA(E_SEND_DATA);
        DUT.E_SEND_DATA(E_SEND_DATA);
        //DUT.TICKIN_TX(TICKIN_TX);
 
        //DUT.TIMEIN_CONTROL_FLAG_TX(TIMEIN_CONTROL_FLAG_TX);
 
        //DUT.TXWRITE_TX(TXWRITE_TX);
 
        //DUT.TXDATA_FLAGCTRL_TX(TXDATA_FLAGCTRL_TX);
 
        DUT.FSM_TX(FSM_TX);
        DUT.FSM_TX(FSM_TX);
        //DUT.READY_TX(READY_TX);
 
        //DUT.READY_TICK(READY_TICK);
 
        DUT.DOUT(DOUT);
        DUT.DOUT(DOUT);
        DUT.SOUT(SOUT);
        DUT.SOUT(SOUT);
 
 
        DUT.DIN(DIN);
        DUT.DIN(DIN);
        DUT.SIN(SIN);
        DUT.SIN(SIN);
Line 359... Line 305...
        else
        else
        {
        {
                enable_time_code_verilog = false;
                enable_time_code_verilog = false;
        }
        }
 
 
        /*
 
        data_generated.clear();
 
        data_iteration=0;
 
        data_iteration_vlog=0;
 
        if(CheckBtnEop->get_active())
 
        {
 
                for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
 
                {
 
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
 
                        {
 
                                intermediate(8,8) = 1;
 
                                intermediate(7,0) = 0;
 
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
 
                        {
 
                                intermediate(7,0) = data_in(rd);
 
                                intermediate(8,8) = 0;
 
                        }
 
                        data_generated.push_back(intermediate);
 
                }
 
                start_send_data_verilog = true;
 
        }else if(CheckBtnEep->get_active())
 
        {
 
                for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
 
                {
 
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
 
                        {
 
                                intermediate(8,8) = 1;
 
                                intermediate(7,0) = 1;
 
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
 
                        {
 
                                intermediate(7,0) = data_in(rd);
 
                                intermediate(8,8) = 0;
 
                        }
 
                        data_generated.push_back(intermediate);
 
                }
 
                intermediate(7,0) = 1;
 
                intermediate(8,8) = 1;
 
                data_generated[nchar(rd)] = intermediate;
 
                start_send_data_verilog = true;
 
        }
 
 
 
        if(CheckBtnTimeCode->get_active())
 
        {
 
                enable_time_code_verilog = true;
 
        }
 
        */
 
 
 
 
 
}
}
 
 
void on_BtnGenerationDataVerilog_clicked()
void on_BtnGenerationDataVerilog_clicked()
{
{
        data_generated_verilog.clear();
        data_generated_verilog.clear();
        data_iteration=0;
        data_iteration=0;
        data_iteration_vlog=0;
        data_iteration_vlog=0;
        if(CheckBtnEopGenVerilog->get_active())
        if(CheckBtnEopGenVerilog->get_active())
        {
        {
                for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
                for(int cnt_max_data = 0; cnt_max_data < max_data;cnt_max_data++)
                {
 
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
 
                        {
                        {
                                intermediate_verilog(8,8) = 1;
                        if(cnt_max_data >= 0 && cnt_max_data < max_data)
                                intermediate_verilog(7,0) = 0;
 
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
 
                        {
                        {
                                intermediate_verilog(7,0) = data_in(rd);
                                intermediate_verilog(7,0) = data_in(rd);
                                intermediate_verilog(8,8) = 0;
                                intermediate_verilog(8,8) = 0;
                        }
 
                        data_generated_verilog.push_back(intermediate_verilog);
                        data_generated_verilog.push_back(intermediate_verilog);
                }
                }
 
                        intermediate_verilog=0;
 
 
 
                }
 
 
 
                intermediate_verilog(8,8) = 1;
 
                intermediate_verilog(7,0) = 0;
 
 
 
                data_generated_verilog.push_back(intermediate_verilog);
 
                intermediate_verilog=0;
        }else if(CheckBtnEepGenVerilog->get_active())
        }else if(CheckBtnEepGenVerilog->get_active())
        {
        {
                for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
                for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
                {
                {
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
Line 442... Line 345...
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
                        {
                        {
                                intermediate_verilog(7,0) = data_in(rd);
                                intermediate_verilog(7,0) = data_in(rd);
                                intermediate_verilog(8,8) = 0;
                                intermediate_verilog(8,8) = 0;
                        }
                        }
 
                        else
 
                        {
 
                                intermediate_verilog(7,0) = data_in(rd);
 
                                intermediate_verilog(8,8) = 0;
 
                        }
                        data_generated_verilog.push_back(intermediate_verilog);
                        data_generated_verilog.push_back(intermediate_verilog);
 
                        intermediate_verilog=0;
                }
                }
                intermediate_verilog(7,0) = 1;
                intermediate_verilog(7,0) = 1;
                intermediate_verilog(8,8) = 1;
                intermediate_verilog(8,8) = 1;
                data_generated_verilog[nchar(rd)] = intermediate_verilog;
                data_generated_verilog[nchar(rd)] = intermediate_verilog;
        }
        }
Line 525... Line 434...
        data_generated_sc.clear();
        data_generated_sc.clear();
        data_iteration_sc_aux=0;
        data_iteration_sc_aux=0;
        data_iteration_sc=0;
        data_iteration_sc=0;
        if(CheckBtnEopGenSystemC->get_active())
        if(CheckBtnEopGenSystemC->get_active())
        {
        {
                for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
                for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
                {
 
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
 
                        {
                        {
                                intermediate_sc(8,8) = 1;
                        if(cnt_max_data > 0 && cnt_max_data < max_data)
                                intermediate_sc(7,0) = 0;
 
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
 
                        {
                        {
                                intermediate_sc(7,0) = data_in(rd);
                                intermediate_sc(7,0) = data_in(rd);
                                intermediate_sc(8,8) = 0;
                                intermediate_sc(8,8) = 0;
                        }
                        }
                        data_generated_sc.push_back(intermediate_sc);
                        data_generated_sc.push_back(intermediate_sc);
                }
                }
 
 
 
                intermediate_sc(8,8) = 1;
 
                intermediate_sc(7,0) = 0;
 
 
 
                data_generated_sc.push_back(intermediate_verilog);
 
                intermediate_sc=0;
 
 
        }else if(CheckBtnEepGenSystemC->get_active())
        }else if(CheckBtnEepGenSystemC->get_active())
        {
        {
                for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
                for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
                {
                {
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
Line 706... Line 618...
 
 
        sn_top->E_SEND_DATA = false;
        sn_top->E_SEND_DATA = false;
 
 
        sn_top->CLOCK_GEN = 1;
        sn_top->CLOCK_GEN = 1;
        frquency_nano_second = 500;
        frquency_nano_second = 500;
        //sn_top->TICKIN_TX = false;
 
        //sn_top->TIMEIN_CONTROL_FLAG_TX = 0;
 
 
 
        //sn_top->TXWRITE_TX = false;
 
        //sn_top->TXDATA_FLAGCTRL_TX = 0;
 
}
}
 
 
void autostart()
void autostart()
{
{
        if(auto_start)
        if(auto_start)
Line 868... Line 775...
void Control_SC::end_tx_test()
void Control_SC::end_tx_test()
{
{
        start_send_data_verilog = enable_time_code_verilog = false;
        start_send_data_verilog = enable_time_code_verilog = false;
}
}
 
 
int Control_SC::size_data_test()
int Control_SC::size_data_test_vlog()
 
{
 
        return data_generated_verilog.size();
 
}
 
 
 
int Control_SC::size_data_test_sc()
{
{
        return data_generated_verilog.size()-1;
        return data_generated_sc.size();
}
}
 
 
unsigned int Control_SC::take_data(unsigned int a)
unsigned int Control_SC::take_data(unsigned int a)
{
{
        intermediate = data_generated_verilog[a];
        intermediate = data_generated_verilog[a];
Line 905... Line 817...
                {
                {
                        data_iteration_sc = 0;
                        data_iteration_sc = 0;
                }
                }
}
}
 
 
 
 
 
void  Control_SC::data_rx_vlog_loopback_o(unsigned int data, unsigned int pos)
 
{
 
 
 
        sc_uint<9> intermediate;
 
 
 
        data_col_store.clear();
 
 
 
        data_col_store.push_back("DATA");
 
        intermediate = data_generated_verilog[pos];
 
        data_col_store.push_back(intermediate.to_string(SC_HEX));
 
 
 
        intermediate = data;
 
        data_col_store.push_back(intermediate(8,0).to_string(SC_HEX));
 
        data_col_store.push_back(" ");
 
        COMPARE_SPW->compare_test(&data_col_store);
 
 
 
        data_col_store.push_back(sc_time_stamp().to_string());
 
        REC_TX_SPW->storedata(data_col_store);
 
}
 
 
 
void data_rx_sc_o(unsigned int type_char, sc_uint<4> control, sc_uint<4> last_control_sys , sc_uint<10> data , sc_uint<10> timecode_sys)
 
{
 
        data_col_store.clear();
 
 
 
        switch(type_char)
 
        {
 
                case 0:
 
                        data_col_store.push_back("NULL");
 
                        data_col_store.push_back(" - ");
 
                        data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
 
                        data_col_store.push_back(" - ");
 
                        data_col_store.push_back(sc_time_stamp().to_string());
 
                        REC_TX_SPW->storedata(data_col_store);
 
                break;
 
                case 1:
 
                        data_col_store.push_back("FCT");
 
                        data_col_store.push_back(" - ");
 
                        data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
 
                        data_col_store.push_back(" - ");
 
                        data_col_store.push_back(sc_time_stamp().to_string());
 
                        REC_TX_SPW->storedata(data_col_store);
 
                break;
 
                case 2:
 
                        data_col_store.push_back("EOP");
 
                        intermediate_data = data_generated_verilog[data_iteration];
 
                        data_col_store.push_back(intermediate_data.to_string(SC_HEX));
 
                        data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
 
                        data_col_store.push_back(" ");
 
                        COMPARE_SPW->compare_test(&data_col_store);
 
                        data_iteration++;
 
                        data_col_store.push_back(sc_time_stamp().to_string());
 
                        REC_TX_SPW->storedata(data_col_store);
 
                break;
 
                case 3:
 
                        data_col_store.push_back("EEP");
 
                        intermediate_data = data_generated_verilog[data_iteration];
 
                        data_col_store.push_back(intermediate_data.to_string(SC_HEX));
 
 
 
                        data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
 
                        data_col_store.push_back(" ");
 
                        COMPARE_SPW->compare_test(&data_col_store);
 
                        data_iteration++;
 
 
 
                        data_col_store.push_back(sc_time_stamp().to_string());
 
                        REC_TX_SPW->storedata(data_col_store);
 
                break;
 
                case 4:
 
                        data_col_store.push_back("INVALID CONNECTION");
 
                        data_col_store.push_back(" - ");
 
                        data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
 
                        data_col_store.push_back(" - ");
 
                        data_col_store.push_back(sc_time_stamp().to_string());
 
                        REC_TX_SPW->storedata(data_col_store);
 
                break;
 
                case 5:
 
                        data_col_store.push_back("DATA");
 
                        intermediate_data = data_generated_verilog[data_iteration];
 
                        data_col_store.push_back(intermediate_data.to_string(SC_HEX));
 
 
 
                        data_col_store.push_back(data(8,0).to_string(SC_HEX));
 
                        data_col_store.push_back(" ");
 
                        COMPARE_SPW->compare_test(&data_col_store);
 
 
 
                        data_col_store.push_back(sc_time_stamp().to_string());
 
                        REC_TX_SPW->storedata(data_col_store);
 
                        data_iteration++;
 
                break;
 
                case 6:
 
                        data_col_store.push_back("TIMECODE");
 
                        data_col_store.push_back(" - ");
 
                        data_col_store.push_back(timecode_sys(7,0).to_string());
 
                        data_col_store.push_back(" - ");
 
                        data_col_store.push_back(sc_time_stamp().to_string());
 
                        REC_TX_SPW->storedata(data_col_store);
 
                break;
 
        }
 
 
 
}
 
 
unsigned int Control_SC::clock_tx()
unsigned int Control_SC::clock_tx()
{
{
        return sn_top->DUT.CLOCK_TX_OUT.read();
        return sn_top->DUT.CLOCK_TX_OUT.read();
}
}
 
 

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