URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [testbench/] [module_tb.v] - Diff between revs 7 and 12

Rev 7	Rev 12
Line 148...	Line 148...
`begin`	`begin`
`$dumpfile("module_tb.vcd");`	`$dumpfile("module_tb.vcd");`
`$dumpvars(0,module_tb);`	`$dumpvars(0,module_tb);`
`$global_init;`	`$global_init;`
`i=0;`	`i=0;`
	`time_clk_ns = 500;`
`end`	`end`

`initial PCLK = 1'b0;`	`initial PCLK = 1'b0;`
`always #(5) PCLK = ~PCLK;`	`always #(5) PCLK = ~PCLK;`

`initial PPLLCLK = 1'b0;`	`initial PPLLCLK = 1'b0;`
`always #(100) PPLLCLK = ~PPLLCLK;`	`always #(time_clk_ns/2) PPLLCLK = ~PPLLCLK;`

`initial CLK_SIM = 1'b0;`	`initial CLK_SIM = 1'b0;`
`always #(1) CLK_SIM = ~CLK_SIM;`	`always #(1) CLK_SIM = ~CLK_SIM;`


Line 196...	Line 197...
`.top_tx_ready_tick(TOP_TX_READY_TICK),`	`.top_tx_ready_tick(TOP_TX_READY_TICK),`

`.top_fsm(TOP_FSM)`	`.top_fsm(TOP_FSM)`
`);`	`);`




`//`	`//`
`always@(posedge PCLK)`	`always@(posedge PCLK)`
`$write_tx_fsm_spw_ultra_light;`	`$write_tx_fsm_spw_ultra_light;`

`//`	`//`
`always@(posedge PCLK)`	`always@(posedge PCLK or posedge TOP_TX_READY)`
`$write_tx_data_spw_ultra_light;`	`$write_tx_data_spw_ultra_light;`

`always@(posedge PCLK)`	`always@(posedge PCLK)`
`$write_tx_time_code_spw_ultra_light;`	`$write_tx_time_code_spw_ultra_light;`