URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [testbench/] [module_tb.v] - Diff between revs 5 and 7

Rev 5	Rev 7
Line 133...	Line 133...
`wire TOP_TX_READY;`	`wire TOP_TX_READY;`
`wire TOP_TX_READY_TICK;`	`wire TOP_TX_READY_TICK;`

`wire [5:0] TOP_FSM;`	`wire [5:0] TOP_FSM;`

	`wire TX_CLOCK_RECOVERY_VLOG;`
	`wire [3:0] SPW_SC_FSM;`
	`wire [3:0] SPW_SC_FSM_OUT;`

	`assign TX_CLOCK_RECOVERY_VLOG = TOP_DOUT ^ TOP_SOUT;`
	`assign SPW_SC_FSM_OUT = SPW_SC_FSM;`

`integer i;`	`integer i;`

`initial`	`initial`
`begin`	`begin`
`$dumpfile("module_tb.vcd");`	`$dumpfile("module_tb.vcd");`
Line 204...	Line 211...

`always@(posedge PCLK)`	`always@(posedge PCLK)`
`$write_tx_time_code_spw_ultra_light;`	`$write_tx_time_code_spw_ultra_light;`

`//`	`//`
`always@(posedge PCLK)`	`always@(posedge BUFFER_WRITE)`
`$receive_rx_data_spw_ultra_light;`	`$receive_rx_data_spw_ultra_light;`

`always@(posedge PCLK)`	`always@(posedge TICK_OUT)`
`$receive_rx_time_code_spw_ultra_light;`	`$receive_rx_time_code_spw_ultra_light;`

`//`	`//`
`always@(posedge PCLK , negedge PCLK)`	`always@(posedge PCLK , negedge PCLK)`
`$global_reset;`	`$global_reset;`

`//`	`//`
`always@(posedge CLK_SIM)`	`always@(posedge CLK_SIM)`
`$run_sim;`	`$run_sim;`

`//FLAG USED TO FINISH SIMULATION PROGRAM`	`//FLAG USED TO FINISH SIMULATION PROGRAM`